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Conv TTL Blocking - Gateware
Commit 5ff8b951 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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updated docs and changed fwvers 

- hdlguide: added info about pulse rejection
- userguide: corrected channel delay when glitch filt enabled (40ns ->
  56 ns)
- changed firmware version in release top-level file
parent 23cf4ac4
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doc/hdlguide/fig/pulse-gen.svg
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doc/hdlguide/hdlguide-conv-ttl-blo.tex
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...@@ -42,6 +42,7 @@ ...@@ -42,6 +42,7 @@
\hline \hline
04-07-2013 & 0.1 & First draft \\ 04-07-2013 & 0.1 & First draft \\
26-07-2013 & 0.2 & Second draft \\ 26-07-2013 & 0.2 & Second draft \\
05-08-2013 & 0.3 & Added pulse rejection to \textit{ctb\_pulse\_gen} \\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -360,7 +361,7 @@ multiplexers are set throughout the logic. ...@@ -360,7 +361,7 @@ multiplexers are set throughout the logic.
% SEC: Pulse gen % SEC: Pulse gen
%============================================================================== %==============================================================================
\pagebreak \pagebreak
\section{Pulse generators} \section{Pulse generator}
\label{sec:pulse-gen} \label{sec:pulse-gen}
%\begin{table}[h] %\begin{table}[h]
...@@ -370,17 +371,16 @@ multiplexers are set throughout the logic. ...@@ -370,17 +371,16 @@ multiplexers are set throughout the logic.
{ {
\begin{tabular}{l l l} \begin{tabular}{l l l}
\hline \hline
\textbf{Entity} & \textit{ctb\_pulse\_gen} & \\ \textbf{Entity} & \textit{ctb\_pulse\_gen} & \\
\textbf{Generics} & \textit{g\_pulse\_width} & Width of the output pulse in \textit{clk\_i} cycles \\ \textbf{Generics} & \textit{g\_pwidth} & Width of the output pulse in \textit{clk\_i} cycles \\
& \textit{g\_glitch\_filt\_len} & Length of glitch filter \\ & \textit{g\_gf\_len} & Length of glitch filter \\
\textbf{Ports} & \textit{clk\_i} & Clock signal \\ \textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_n\_i} & Active-low reset signal \\ & \textit{rst\_n\_i} & Active-low reset signal \\
& \textit{en\_i} & Pulse generator enable \\ & \textit{en\_i} & Pulse generator enable \\
& \textit{glitch\_filt\_en\_n} & Active-low glitch filter enable \\ & \textit{gf\_en\_n\_i} & Active-low glitch filter enable \\
& \textit{trig\_i} & Pulse trigger \\ & \textit{trig\_i} & Pulse trigger \\
& \textit{pulse\_o} & Pulse output \\ & \textit{pulse\_o} & Pulse output \\
\textbf{Usage} & Output pulse & 1.2~${\mu}s$ pulses \\ \textbf{Usage} & Output pulse & 1.2~$\mu$s pulses with min. period of 6~$\mu$s\\
& Flash pulse LEDs & 96~$ms$ pulses \\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -388,23 +388,18 @@ multiplexers are set throughout the logic. ...@@ -388,23 +388,18 @@ multiplexers are set throughout the logic.
\vspace*{11pt} \vspace*{11pt}
The \textit{ctb\_pulse\_gen} block generate pulses on the rising edge of the The \textit{ctb\_pulse\_gen} block generates pulses on the rising edge of the
\textit{trig\_i} input. The pulse width is configurable via the \textit{g\_pulse\_width} \textit{trig\_i} input. The pulse width is configurable via the \textit{g\_pwidth}
generic. The block also incorporates a glitch filter with a configurable length generic. The block also incorporates a glitch filter with a configurable length
(\textit{g\_glitch\_filt\_len}) that can be used to avoid pulses generated because of (\textit{g\_gf\_len}) that can be used to avoid pulses generated because of
glitches at the \textit{trig\_i} input. glitches at the \textit{trig\_i} input.
These blocks are twice used in the CONV-TTL-BLO firmware. First, they are used for Pulse widths at the output are limited internally to 1/5 duty cycle, to safeguard
generating the output pulses based on the trigger input. In this case, they are configured the blocking output transformers.
for 1.2~${\mu}s$ pulses (\textit{g\_pulse\_width = 150}, considering the 8~$ns$ clock input).
Second, they are used for blinking the front and rear-panel pulse LEDs Six \textit{ctb\_pulse\_gen} blocks (one per channel) are used for generating blocking and TTL
when a pulse is generated. In this second case, the pulse generator blocks are pulses at the outputs, based on trigger inputs arriving on the channels. The \textit{ctb\_pulse\_gen} blocks
configured to generate 96~$ms$ pulses (\textit{g\_pulse\_width} $= 12*10^6$), enough are configured for 1.2~${\mu}s$ pulses (\textit{g\_pwidth = 150}, considering the 8~$ns$ clock input).
to be visible to the human eye.
In both cases, the logic associated to the blocks is multiplied by six, since
there are six replication channels.
%------------------------------------------------------------------------------ %------------------------------------------------------------------------------
% SUBSEC: Implem % SUBSEC: Implem
...@@ -413,7 +408,7 @@ there are six replication channels. ...@@ -413,7 +408,7 @@ there are six replication channels.
\label{sec:pulse-gen-implem} \label{sec:pulse-gen-implem}
Figure~\ref{fig:pulse-gen} shows the implementation of the \textit{ctb\_pulse\_gen} Figure~\ref{fig:pulse-gen} shows the implementation of the \textit{ctb\_pulse\_gen}
block. It employs a counter finite-state machine (FSM) that is used to generate block. It employs a finite-state machine (FSM) that is used to generate
a fixed-width pulse at the output. a fixed-width pulse at the output.
\begin{figure}[h] \begin{figure}[h]
...@@ -422,29 +417,34 @@ a fixed-width pulse at the output. ...@@ -422,29 +417,34 @@ a fixed-width pulse at the output.
\label{fig:pulse-gen} \label{fig:pulse-gen}
\end{figure} \end{figure}
The block contains a glitch filter that can be used to decrease sensitivity to glitches The glitch filter can be used to decrease sensitivity to glitches in noisy environments.
in noisy environments. The glitch filter length can be enabled via the It can be enabled via the \textit{gf\_en\_n\_i} input (connected to SW1.1 on the CONV-TTL-BLO).
\textit{glitch\_filt\_en\_n} input (connected to SW1.1 on the CONV-TTL-BLO). The length The length of the filter can be set via the \textit{g\_gf\_len} generic.
of the filter can be set via the \textit{g\_glitch\_filt\_len} generic.
Enabling the glitch filter will lead to the trigger being sampled using \textit{clk125} Enabling the glitch filter will lead to the trigger being sampled using \textit{clk125}
and introduces leading-edge jitter on the \textit{pulse\_o} output. To avoid this and introduces leading-edge jitter on the \textit{pulse\_o} output. To avoid this
leading-edge pulse jitter, the glitch filter can be disabled. leading-edge pulse jitter, the glitch filter can be left disabled.
Regardless of whether the glitch filter is enabled or not, the FSM reacts to the Regardless of whether the glitch filter is enabled or not, the FSM reacts to the
rising edge of one of its two start inputs. A rising edge on an input starts rising edge of one of its two start inputs. A rising edge on an input starts
the internal counter, which counts up to a maximum value of \textit{g\_pulse\_width}. the internal counter, which counts up to a maximum value of \textit{g\_pwidth}.
The behavior of the outputs are different, depending on the state of the glitch filter. The behavior of the outputs are different, depending on the state of the glitch filter.
With the glitch filter disabled, the input pulse enables the With the glitch filter disabled, the input pulse enables the
input flip-flop, which starts pulse generation. The pulse signal is then synchronized input flip-flop, which starts pulse generation. The pulse signal is then synchronized
in the \textit{clk125} domain and input to the synchronous counter FSM. The rising in the \textit{clk125} domain and input to the synchronous FSM, which extends the
edge on \textit{SGF0} triggers the counter, and when the counter reaches the maximum pulse to \textit{g\_pwidth}. The rising edge on \textit{SGF0} triggers the counter,
value it sets the \textit{OGF0} output for one clock cycle, which will reset the and when the counter reaches the value corresponding to the selected pulse width,
input flip-flop, thus ending the pulse. it sets the \textit{OGF0} output, which will reset the input flip-flop, thus ending the pulse.
With the glitch filter enabled, the rising edge on \textit{SGF1} sets \textit{OGF1}, With the glitch filter enabled, the rising edge on \textit{SGF1} sets \textit{OGF1},
and this will be kept high until the counter reaches the maximum value. and this will be kept high until the counter reaches the value corresponding to the
pulse width.
After the pulse generation period, the FSM goes into a pulse rejection state,
where the pulse reset is kept high. If any pulses arrive on the input while the FSM
is in this rejection state, they are not replicated at the output. The pulse rejection
phase lasts for 4*\textit{g\_pwidth}, yielding a maximum duty cycle of 1/5 for input pulses.
%------------------------------------------------------------------------------ %------------------------------------------------------------------------------
% SUBSEC: Board-level % SUBSEC: Board-level
...@@ -691,7 +691,7 @@ following sections list the memory map of each peripheral. ...@@ -691,7 +691,7 @@ following sections list the memory map of each peripheral.
%------------------------------------------------------------------------------ %------------------------------------------------------------------------------
% APP: CSR % APP: CSR
%------------------------------------------------------------------------------ %------------------------------------------------------------------------------
\section{Control and status registers} \subsection{Control and status registers}
\label{app:memmap-csr} \label{app:memmap-csr}
\indent Base address: 0x000 \indent Base address: 0x000
...@@ -709,7 +709,7 @@ following sections list the memory map of each peripheral. ...@@ -709,7 +709,7 @@ following sections list the memory map of each peripheral.
\noindent Reserved addresses read undefined and should be written as 0x00000000. \noindent Reserved addresses read undefined and should be written as 0x00000000.
%------------------------------------------------------------------------------ %------------------------------------------------------------------------------
\subsection{Board ID register} \subsubsection{Board ID register}
\begin{tabular}{l l c c l} \begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\ \textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
...@@ -727,7 +727,7 @@ following sections list the memory map of each peripheral. ...@@ -727,7 +727,7 @@ following sections list the memory map of each peripheral.
} }
%------------------------------------------------------------------------------ %------------------------------------------------------------------------------
\subsection{Status register} \subsubsection{Status register}
\begin{tabular}{l l c c l} \begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\ \textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
...@@ -742,7 +742,7 @@ following sections list the memory map of each peripheral. ...@@ -742,7 +742,7 @@ following sections list the memory map of each peripheral.
\begin{tabular}{l p{.8\textwidth}} \begin{tabular}{l p{.8\textwidth}}
\textbf{Field} & \textbf{Description} \\ \textbf{Field} & \textbf{Description} \\
\textit{fwvers} & Firmware version \textit{fwvers} & Firmware version \newline
-- leftmost byte \textit{hex value} is major release \textit{decimal value} \newline -- leftmost byte \textit{hex value} is major release \textit{decimal value} \newline
-- rightmost byte \textit{hex value} is minor release \textit{decimal value} \newline -- rightmost byte \textit{hex value} is minor release \textit{decimal value} \newline
e.g. \newline e.g. \newline
......
doc/userguide/userguide-conv-ttl-blo.tex
View file @ 5ff8b951
...@@ -43,6 +43,7 @@ ...@@ -43,6 +43,7 @@
21-06-2013 & 1.01 & Added termination resistors to Fig.~\ref{fig:ttl-chan},~\ref{fig:invttl-chan} \\ 21-06-2013 & 1.01 & Added termination resistors to Fig.~\ref{fig:ttl-chan},~\ref{fig:invttl-chan} \\
22-07-2013 & 1.02 & New title page and page layout \\ 22-07-2013 & 1.02 & New title page and page layout \\
26-07-2013 & 1.03 & Added additional documentation subsection \\ 26-07-2013 & 1.03 & Added additional documentation subsection \\
05-08-2013 & 1.04 & Memory map is now appendix \\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -554,7 +555,7 @@ the CONV-TTL-BLO. ...@@ -554,7 +555,7 @@ the CONV-TTL-BLO.
} }
\end{table} \end{table}
\noindent Note 1: If glitch filter is enabled, it adds an extra 40~ns delay to $t_{PD}$. \noindent Note 1: If glitch filter is enabled, it adds an extra 56~ns delay to $t_{PD}$.
%====================================================================================== %======================================================================================
% SEC: Communicating to the CONV-TTL-BLO % SEC: Communicating to the CONV-TTL-BLO
...@@ -566,23 +567,17 @@ the CONV-TTL-BLO. ...@@ -566,23 +567,17 @@ the CONV-TTL-BLO.
It is possible to communicate to the CONV-TTL-BLO remotely via the VME P1 I$^2$C interface. It is possible to communicate to the CONV-TTL-BLO remotely via the VME P1 I$^2$C interface.
This section describes how to connect to the VME64x crate and communicate to the board. This section describes how to connect to the VME64x crate and communicate to the board.
%--------------------------------------------------------------------------------------
% SUBSEC: ELMA I2C
%--------------------------------------------------------------------------------------
\subsection{The ELMA I$^2$C protocol}
\label{sec:comm-elma-prot}
In order to connect to a CONV-TTL-BLO board in an ELMA VME crate, a higher-level In order to connect to a CONV-TTL-BLO board in an ELMA VME crate, a higher-level
protocol based on I$^2$C is defined \cite{sysmon-i2c}. The protocol uses the serial protocol based on I$^2$C is defined \cite{sysmon-i2c}. The protocol uses the serial
lines on the VME P1 connector (\textit{SERCLK}, \textit{SERDAT}). lines on the VME P1 connector (\textit{SERCLK}, \textit{SERDAT}).
By this protocol, 2$^{12}$ (12 address bits) 32-bit registers can be read from or written By this protocol, 2$^{12}$ (12 address bits) 32-bit registers can be read from or written
to byte by byte. The user accesses the VME crate using Telnet and sends commands to byte by byte. A complete memory map for accessible registers can be found in Appendix~\ref{app:memmap}.
which the ELMA SysMon board translates to I$^2$C transfers to the board.
Two telnet commands (see Table~\ref{tbl:rwreg}) can be used to transfer data to the board. The user accesses the VME crate using Telnet and sends commands which the ELMA SysMon board
As their names suggest, \textit{readreg} reads a board register, whereas \textit{writereg} translates to I$^2$C transfers to the board. Two telnet commands (see Table~\ref{tbl:rwreg})
writes to a board register. can be used to transfer data to the board. As their names suggest, \textit{readreg} reads a board
register, whereas \textit{writereg} writes to a board register.
\begin{table}[htbp] \begin{table}[htbp]
\caption{The \textit{readreg} and \textit{writereg} commands} \caption{The \textit{readreg} and \textit{writereg} commands}
...@@ -645,33 +640,6 @@ password:********** ...@@ -645,33 +640,6 @@ password:**********
%> %>
\end{verbatim} \end{verbatim}
%--------------------------------------------------------------------------------------
% SUBSEC: Memory map
%--------------------------------------------------------------------------------------
\subsection{Memory map}
\label{sec:comm-memmap}
The memory map of registers accessible through the ELMA protocol is given in Table~\ref{tbl:memmap}.
\begin{table}[htbp]
\caption{CONV-TTL-BLO memory map}
\label{tbl:memmap}
\centerline
{
\begin{tabular}{l r p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Address}} & \multicolumn{1}{c}{\textbf{ELMA reg}}
& \multicolumn{1}{c}{\textbf{Description}} \\
\hline
0x000 & 1 & Board ID register \newline
\textit{access}: R/W \newline
\textit{default}: 0x424C4F32 (ASCII \textbf{BLO2}) \\
\hline
\end{tabular}
}
\end{table}
%====================================================================================== %======================================================================================
% Appendices % Appendices
%====================================================================================== %======================================================================================
...@@ -739,8 +707,8 @@ Blocking pulses arriving on CH1 then get replicated through the daisy chain from ...@@ -739,8 +707,8 @@ Blocking pulses arriving on CH1 then get replicated through the daisy chain from
By connecting all outputs of channels 1 through 4 on the rear panel, the desired pulse By connecting all outputs of channels 1 through 4 on the rear panel, the desired pulse
conversion system can be obtained. conversion system can be obtained.
Each channel will add a 40~ns delay (80~ns with glitch filter), in addition to the 160~ns (240~ns Each channel will add a 40~ns delay (96~ns with glitch filter), in addition to the 160~ns (272~ns
with glitch filter) of the CH1 and CH4 blocking conversions. with glitch filters) of the CH1 and CH4 blocking conversions.
\begin{figure}[h] \begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/ex-blo-rep}} \centerline{\includegraphics[width=\textwidth]{fig/ex-blo-rep}}
...@@ -768,7 +736,106 @@ The inverter channel will add a 30~ns delay to the input TTL signal. ...@@ -768,7 +736,106 @@ The inverter channel will add a 30~ns delay to the input TTL signal.
\label{fig:ex-invert-ttl} \label{fig:ex-invert-ttl}
\end{figure} \end{figure}
%------------------------------------------------------------------------------
% APP: Memmap
%------------------------------------------------------------------------------
\section{Memory map}
\label{app:memmap}
Table~\ref{tbl:memmap} shows the complete memory map of the firmware. The
following sections list the memory map of each peripheral.
\begin{table}[h]
\caption{CONV-TTL-BLO memory map}
\label{tbl:memmap}
\centerline
{
\begin{tabular}{l l l p{.4\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Periph.}} & \multicolumn{2}{c}{\textbf{Address}} & \multicolumn{1}{c}{\textbf{Description}} \\
& \multicolumn{1}{c}{\textbf{Base}} & \multicolumn{1}{c}{\textbf{End}} & \\
\hline
CSR & 0x000 & 0x010 & Control and status register \\
\hline
\end{tabular}
}
\end{table}
%------------------------------------------------------------------------------
% APP: CSR
%------------------------------------------------------------------------------
\subsection{Control and status registers}
\label{app:memmap-csr}
\indent Base address: 0x000
\begin{table}[h]
\begin{tabular}{l c p{.6\textwidth}}
\textbf{Offset} & \textbf{ELMA reg} & \textbf{Description} \\
0x0 & 1 & Board ID register \\
0x4 & 2 & Status register \\
0x8 & 3 & Reserved \\
0xC & 4 & Reserved \\
\end{tabular}
\end{table}
\noindent Reserved addresses read undefined and should be written as 0x00000000.
%------------------------------------------------------------------------------
\subsubsection{Board ID register}
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
31..0 & \textit{id} & R/O & 0x424c4f32 & Board ID \\
\end{tabular}
\vspace*{11pt}
\noindent
{
\begin{tabular}{l l}
\textbf{Field} & \textbf{Description} \\
\textit{id} & Board ID (ASCII string \textbf{BLO2}) \\
\end{tabular}
}
%------------------------------------------------------------------------------
\subsubsection{Status register}
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
15..0 & \textit{fwvers} & R/O & X & Firmware version \\
23..16 & \textit{switches} & R/O & X & Switch status \\
29..24 & \textit{rtm} & R/O & X & RTM detection lines \\
31..30 & \textit{reserved} & R/O & X & \\
\end{tabular}
\noindent
{
\begin{tabular}{l p{.8\textwidth}}
\textbf{Field} & \textbf{Description} \\
\textit{fwvers} & Firmware version \newline
-- leftmost byte \textit{hex value} is major release \textit{decimal value} \newline
-- rightmost byte \textit{hex value} is minor release \textit{decimal value} \newline
e.g. \newline
0x0101 -- v1.01\newline
0x0107 -- v1.07 \newline
0x0274 -- v2.74 \newline
etc. \\
\textit{switches} & Current switch status \newline
bit 0 -- SW1.1 \newline
bit 1 -- SW1.2 \newline
... \newline
bit 7 -- SW2.4 \newline
\textbf{1} -- switch is \textbf{OFF} \newline
\textbf{0} -- switch is \textbf{ON} \\
\textit{rtm} & RTM detection lines status \newline
\textbf{0} -- line active \newline
\textbf{1} -- line inactive \\
\textit{reserved} & Write as '0'; read undefined \\
\end{tabular}
}
\end{appendices} \end{appendices}
......
hdl/ctb_pulse_gen/rtl/ctb_pulse_gen.vhd
View file @ 5ff8b951
...@@ -288,6 +288,13 @@ begin ...@@ -288,6 +288,13 @@ begin
state <= ST_REJ_GF_OFF; state <= ST_REJ_GF_OFF;
end if; end if;
---------------------------------------------------------------------
-- ST_REJ_GF_OFF
---------------------------------------------------------------------
-- Increment pulse counter to pulse rejection value, while keeping
-- the pulse_rst high. Max pulse rejection value is 5x that of
-- pulse width value, to enable 1/5 duty cycle.
---------------------------------------------------------------------
when ST_REJ_GF_OFF => when ST_REJ_GF_OFF =>
pulse_rst <= '1'; pulse_rst <= '1';
pulse_cnt <= pulse_cnt + 1; pulse_cnt <= pulse_cnt + 1;
...@@ -310,6 +317,13 @@ begin ...@@ -310,6 +317,13 @@ begin
state <= ST_REJ_GF_ON; state <= ST_REJ_GF_ON;
end if; end if;
---------------------------------------------------------------------
-- ST_REJ_GF_ON
---------------------------------------------------------------------
-- Increment pulse counter to pulse rejection value, while keeping
-- the pulse_rst high. Max pulse rejection value is 5x that of
-- pulse width value, to enable 1/5 duty cycle.
---------------------------------------------------------------------
when ST_REJ_GF_ON => when ST_REJ_GF_ON =>
pulse_gf_on <= '0'; pulse_gf_on <= '0';
pulse_rst <= '1'; pulse_rst <= '1';
......
hdl/release/top/conv_ttl_blo_v2.vhd
View file @ 5ff8b951
...@@ -120,7 +120,7 @@ architecture behav of conv_ttl_blo_v2 is ...@@ -120,7 +120,7 @@ architecture behav of conv_ttl_blo_v2 is
-- Constant declarations -- Constant declarations
--============================================================================ --============================================================================
-- Firmware version -- Firmware version
constant c_fwvers : std_logic_vector(15 downto 0) := x"0101"; constant c_fwvers : std_logic_vector(15 downto 0) := x"0102";
-- Number of Wishbone masters and slaves, for wb_crossbar -- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1; constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 1; constant c_nr_slaves : natural := 1;
......
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