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Conv TTL Blocking - Gateware
Commit 30a7e29a authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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test_pulse_regs is now only test_pulse

parent 1a49e95c
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hdl/pulse_gen_gp/rtl/pulse_gen_gp.vhd
View file @ 30a7e29a
...@@ -121,7 +121,7 @@ begin ...@@ -121,7 +121,7 @@ begin
p_delay: process (clk_i) p_delay: process (clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if (rst_n_i = '0') then if (rst_n_i = '0') or (en_i = '0') then
delay_en <= '1'; delay_en <= '1';
delay_cnt <= (others => '0'); delay_cnt <= (others => '0');
elsif (en_i = '1') then elsif (en_i = '1') then
......
hdl/test_pulse_regs/syn/conv_ttl_blo.gise → hdl/test_pulse/syn/conv_ttl_blo.gise
View file @ 30a7e29a
...@@ -72,35 +72,35 @@ ...@@ -72,35 +72,35 @@
</files> </files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"> <transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1376649408" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1376649407"> <transform xil_pn:end_ts="1376671447" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1376671447">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376649408" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1376649408"> <transform xil_pn:end_ts="1376671447" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1376671447">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376649408" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1376649408"> <transform xil_pn:end_ts="1376671447" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1376671447">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376649408" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1376649408"> <transform xil_pn:end_ts="1376671447" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1376671447">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376649408" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1376649408"> <transform xil_pn:end_ts="1376671447" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1376671447">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376649408" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1376649408"> <transform xil_pn:end_ts="1376671447" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1376671447">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376649408" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1376649408"> <transform xil_pn:end_ts="1376671447" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1376671447">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376649430" xil_pn:in_ck="1634203216251964596" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1376649408"> <transform xil_pn:end_ts="1376671470" xil_pn:in_ck="1634203216251964596" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1376671447">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -118,11 +118,11 @@ ...@@ -118,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1376649431" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1376649430"> <transform xil_pn:end_ts="1376671470" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1376671470">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1376649441" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1376649431"> <transform xil_pn:end_ts="1376671480" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1376671470">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
...@@ -131,7 +131,7 @@ ...@@ -131,7 +131,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/> <outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1376649562" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1376649441"> <transform xil_pn:end_ts="1376671548" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1376671480">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
...@@ -144,7 +144,7 @@ ...@@ -144,7 +144,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/> <outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/> <outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1376649633" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1376649562"> <transform xil_pn:end_ts="1376671618" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1376671548">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
...@@ -158,7 +158,7 @@ ...@@ -158,7 +158,7 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/> <outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1376649675" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1376649633"> <transform xil_pn:end_ts="1376671658" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1376671618">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
...@@ -169,7 +169,7 @@ ...@@ -169,7 +169,7 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1376649633" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1376649620"> <transform xil_pn:end_ts="1376671618" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1376671605">
<status xil_pn:value="FailedRun"/> <status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/test_pulse_regs/top/conv_ttl_blo.vhd → hdl/test_pulse/top/conv_ttl_blo.vhd
View file @ 30a7e29a
...@@ -120,7 +120,7 @@ architecture behav of conv_ttl_blo is ...@@ -120,7 +120,7 @@ architecture behav of conv_ttl_blo is
--============================================================================ --============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar -- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1; constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 3; constant c_nr_slaves : natural := 2;
----------------------------------------- -----------------------------------------
-- Memory map -- Memory map
...@@ -132,32 +132,32 @@ architecture behav of conv_ttl_blo is ...@@ -132,32 +132,32 @@ architecture behav of conv_ttl_blo is
-- slave order definitions -- slave order definitions
constant c_slv_pgen_ctrl : natural := 0; constant c_slv_pgen_ctrl : natural := 0;
constant c_slv_pulse_cnt : natural := 1; constant c_slv_pulse_cnt : natural := 1;
constant c_slv_mem : natural := 2; -- constant c_slv_mem : natural := 2;
-- base address definitions -- base address definitions
constant c_addr_pgen_ctrl : t_wishbone_address := x"00000000"; constant c_addr_pgen_ctrl : t_wishbone_address := x"00000000";
constant c_addr_pulse_cnt : t_wishbone_address := x"00000080"; constant c_addr_pulse_cnt : t_wishbone_address := x"00000080";
constant c_addr_mem : t_wishbone_address := x"00000100"; -- constant c_addr_mem : t_wishbone_address := x"00000100";
-- address mask definitions -- address mask definitions
constant c_mask_pgen_ctrl : t_wishbone_address := x"00000FF0"; constant c_mask_pgen_ctrl : t_wishbone_address := x"00000F80";
constant c_mask_pulse_cnt : t_wishbone_address := x"00000F80"; constant c_mask_pulse_cnt : t_wishbone_address := x"00000F80";
constant c_mask_mem : t_wishbone_address := x"00000F00"; -- constant c_mask_mem : t_wishbone_address := x"00000F00";
-- addresses constant for Wishbone crossbar -- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0) constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= ( := (
c_slv_pgen_ctrl => c_addr_pgen_ctrl, c_slv_pgen_ctrl => c_addr_pgen_ctrl,
c_slv_pulse_cnt => c_addr_pulse_cnt, c_slv_pulse_cnt => c_addr_pulse_cnt
c_slv_mem => c_addr_mem -- c_slv_mem => c_addr_mem
); );
-- masks constant for Wishbone crossbar -- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0) constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= ( := (
c_slv_pgen_ctrl => c_mask_pgen_ctrl, c_slv_pgen_ctrl => c_mask_pgen_ctrl,
c_slv_pulse_cnt => c_mask_pulse_cnt, c_slv_pulse_cnt => c_mask_pulse_cnt
c_slv_mem => c_mask_mem --c_slv_mem => c_mask_mem
); );
--============================================================================ --============================================================================
...@@ -540,44 +540,44 @@ begin ...@@ -540,44 +540,44 @@ begin
master_o => xbar_master_out master_o => xbar_master_out
); );
--============================================================================ ----============================================================================
-- Instantiate single-port RAM ---- Instantiate single-port RAM
--============================================================================ ----============================================================================
cmp_memory: generic_spram --cmp_memory: generic_spram
generic map ( -- generic map (
g_data_width => 32, -- g_data_width => 32,
g_size => 2**12 -- g_size => 2**9
) -- )
port map ( -- port map (
rst_n_i => rst_n, -- rst_n_i => rst_n,
clk_i => clk125, -- clk_i => clk125,
bwe_i => (others => '0'), -- bwe_i => (others => '0'),
we_i => ram_we, -- we_i => ram_we,
a_i => xbar_master_out(c_slv_mem).adr(11 downto 0), -- a_i => xbar_master_out(c_slv_mem).adr(10 downto 2),
d_i => xbar_master_out(c_slv_mem).dat, -- d_i => xbar_master_out(c_slv_mem).dat,
q_o => xbar_master_in(c_slv_mem).dat -- q_o => xbar_master_in(c_slv_mem).dat
); -- );
ram_we <= xbar_master_out(c_slv_mem).we and xbar_master_out(c_slv_mem).stb and --ram_we <= xbar_master_out(c_slv_mem).we and xbar_master_out(c_slv_mem).stb and
xbar_master_out(c_slv_mem).cyc; -- xbar_master_out(c_slv_mem).cyc;
xbar_master_in(c_slv_mem).ack <= ram_ack; --xbar_master_in(c_slv_mem).ack <= ram_ack;
xbar_master_in(c_slv_mem).err <= '0'; --xbar_master_in(c_slv_mem).err <= '0';
p_ram_ack : process (clk125) is --p_ram_ack : process (clk125) is
begin --begin
if rising_edge(clk125) then -- if rising_edge(clk125) then
if (rst_n = '0') then -- if (rst_n = '0') then
ram_ack <= '0'; -- ram_ack <= '0';
else -- else
ram_ack <= '0'; -- ram_ack <= '0';
if (xbar_master_out(c_slv_mem).stb = '1') and -- if (xbar_master_out(c_slv_mem).stb = '1') and
(xbar_master_out(c_slv_mem).cyc = '1') then -- (xbar_master_out(c_slv_mem).cyc = '1') then
ram_ack <= '1'; -- ram_ack <= '1';
end if; -- end if;
end if; -- end if;
end if; -- end if;
end process p_ram_ack; --end process p_ram_ack;
--============================================================================ --============================================================================
-- Pulse generation control registers instantiation -- Pulse generation control registers instantiation
...@@ -743,6 +743,9 @@ begin ...@@ -743,6 +743,9 @@ begin
end if; end if;
end process p_pulse_led; end process p_pulse_led;
-- Set the pulse status LED for the channel
pulse_front_led_n_o(i) <= (not pulse_leds(i)) when (ch_en(i) = '1') else '1';
end generate gen_chan_logic; end generate gen_chan_logic;
-- Pulse outputs assignment -- Pulse outputs assignment
...@@ -751,8 +754,6 @@ begin ...@@ -751,8 +754,6 @@ begin
fpga_trig_blo_o <= (others => '0'); fpga_trig_blo_o <= (others => '0');
-- Pulse status LED output assignments -- Pulse status LED output assignments
pulse_front_led_n_o <= (not pulse_leds) when (ttl_oe = '1') else
(others => '1');
pulse_rear_led_n_o <= (others => '1'); pulse_rear_led_n_o <= (others => '1');
--============================================================================ --============================================================================
...@@ -786,6 +787,11 @@ begin ...@@ -786,6 +787,11 @@ begin
pulse_cnt_ch6o_val_i => std_logic_vector(cnt_out(6)) pulse_cnt_ch6o_val_i => std_logic_vector(cnt_out(6))
); );
--============================================================================
-- Inverter outputs assignment
--============================================================================
inv_out_o <= inv_in_n_i;
--============================================================================ --============================================================================
-- Bicolor LED matrix logic -- Bicolor LED matrix logic
--============================================================================ --============================================================================
...@@ -817,7 +823,8 @@ begin ...@@ -817,7 +823,8 @@ begin
c_LED_OFF; c_LED_OFF;
-- State of TTL/TTL_N switch -- State of TTL/TTL_N switch
bicolor_led_state(15 downto 14) <= c_LED_OFF; bicolor_led_state(15 downto 14) <= c_LED_GREEN when (ttl_switch_n_i = '0') else
c_LED_OFF;
-- System error -- System error
bicolor_led_state(17 downto 16) <= c_LED_OFF; bicolor_led_state(17 downto 16) <= c_LED_OFF;
......
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