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Conv TTL Blocking - Gateware
Commit 29b287b7 authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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m25p32 fsm small modifications to look like Xilinx examples: added some extra… 

m25p32 fsm small modifications to look like Xilinx examples: added some extra NOOPs and butterfly reassignment between s_icap_tmp and s_icap_i
parent c2453b50
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hdl/multiboot/rtl/multiboot_core.vhd
View file @ 29b287b7
......@@ -30,6 +30,7 @@ architecture Behavioral of multiboot_core is
S1B_READBACK);
--! The fsm for multiboot can be found in ug380 pg126
--! Added four noop states as it is done in example xt059.pdf
type multi_ICAP_fsm is (R0_RESET,
S0_IDLE,
S1_DUMMY,
......@@ -45,6 +46,10 @@ architecture Behavioral of multiboot_core is
S11_GEN4_ADDR,
S12_CMD_CMD,
S13_IPROG,
S14_NOOP,
S15_NOOP,
S16_NOOP,
S17_NOOP,
Q0_OK);
--! The fsm for readbacks can be found in ug380 pg109
......@@ -78,6 +83,7 @@ architecture Behavioral of multiboot_core is
signal s_icap_o : STD_LOGIC_VECTOR(15 downto 0);
signal s_icap_ce_n : STD_LOGIC := '1'; --! Enable in ICAP is active low
signal s_icap_i : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal s_icap_tmp : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal s_icap_wr_n : STD_LOGIC := '1';
signal s_CTR0 : r_CTR0;
......@@ -108,6 +114,7 @@ begin
s_GBA <= GBA_i;
MBA_ICAP_o <= s_MBA_ICAP;
GBA_ICAP_o <= s_GBA_ICAP;
order_ICAP(s_icap_tmp, s_icap_i);
ICAP_SPARTAN6_inst : ICAP_SPARTAN6
generic map (-- Pre-programmed 'Device ID code'
......@@ -301,7 +308,7 @@ begin
s_multiboot_fsm,
s_readback_fsm)
begin
s_icap_i <= NULL_value;
s_icap_tmp <= NULL_value;
case s_ICAP_fsm is
when S1A_MULTIBOOT =>
case s_multiboot_fsm is
......@@ -310,31 +317,39 @@ begin
when S0_IDLE =>
null;
when S1_DUMMY =>
s_icap_i <= DUMMY;
s_icap_tmp <= DUMMY;
when S2_SYNC_H =>
s_icap_i <= SYNC_H;
s_icap_tmp <= SYNC_H;
when S3_SYNC_L =>
s_icap_i <= SYNC_L;
s_icap_tmp <= SYNC_L;
when S4_GEN1_CMD =>
s_icap_i <= CMD_wr_GEN1;
s_icap_tmp <= CMD_wr_GEN1;
when S5_GEN1_ADDR =>
s_icap_i <= s_wr_ICAP_gen1;
s_icap_tmp <= s_wr_ICAP_gen1;
when S6_GEN2_CMD =>
s_icap_i <= CMD_wr_GEN2;
s_icap_tmp <= CMD_wr_GEN2;
when S7_GEN2_ADDR =>
s_icap_i <= s_wr_ICAP_gen2;
s_icap_tmp <= s_wr_ICAP_gen2;
when S8_GEN3_CMD =>
s_icap_i <= CMD_wr_GEN3;
s_icap_tmp <= CMD_wr_GEN3;
when S9_GEN3_ADDR =>
s_icap_i <= s_wr_ICAP_gen3;
s_icap_tmp <= s_wr_ICAP_gen3;
when S10_GEN4_CMD =>
s_icap_i <= CMD_wr_GEN4;
s_icap_tmp <= CMD_wr_GEN4;
when S11_GEN4_ADDR =>
s_icap_i <= s_wr_ICAP_gen4;
s_icap_tmp <= s_wr_ICAP_gen4;
when S12_CMD_CMD =>
s_icap_i <= CMD_wr_CMD;
s_icap_tmp <= CMD_wr_CMD;
when S13_IPROG =>
s_icap_i <= CMD_IPROG;
s_icap_tmp <= CMD_IPROG;
when S14_NOOP =>
s_icap_tmp <= NOOP;
when S15_NOOP =>
s_icap_tmp <= NOOP;
when S16_NOOP =>
s_icap_tmp <= NOOP;
when S17_NOOP =>
s_icap_tmp <= NOOP;
when Q0_OK =>
null;
when others =>
......@@ -345,47 +360,47 @@ begin
when R0_RESET =>
null;
when S1_DUMMY1 =>
s_icap_i <= DUMMY;
s_icap_tmp <= DUMMY;
when S2_DUMMY2 =>
s_icap_i <= DUMMY;
s_icap_tmp <= DUMMY;
when S3_SYNC_H =>
s_icap_i <= SYNC_H;
s_icap_tmp <= SYNC_H;
when S4_SYNC_L =>
s_icap_i <= SYNC_L;
s_icap_tmp <= SYNC_L;
when S5_NOOP =>
s_icap_i <= NOOP;
s_icap_tmp <= NOOP;
when S6A_READ_CMD =>
s_icap_i <= s_rd_ICAP_regA;
s_icap_tmp <= s_rd_ICAP_regA;
when S7A_NOOP =>
s_icap_i <= NOOP;
s_icap_tmp <= NOOP;
when S8A_NOOP =>
s_icap_i <= NOOP;
s_icap_tmp <= NOOP;
when S9A_NOOP =>
s_icap_i <= NOOP;
s_icap_tmp <= NOOP;
when S10A_NOOP =>
s_icap_i <= NOOP;
s_icap_tmp <= NOOP;
when S11A_FETCH_REG =>
null;
when S6B_READ_CMD =>
s_icap_i <= s_rd_ICAP_regB;
s_icap_tmp <= s_rd_ICAP_regB;
when S7B_NOOP =>
s_icap_i <= NOOP;
s_icap_tmp <= NOOP;
when S8B_NOOP =>
s_icap_i <= NOOP;
s_icap_tmp <= NOOP;
when S9B_NOOP =>
s_icap_i <= NOOP;
s_icap_tmp <= NOOP;
when S10B_NOOP =>
s_icap_i <= NOOP;
s_icap_tmp <= NOOP;
when S11B_FETCH_REG =>
null;
when S12_WRITE_CMD =>
s_icap_i <= CMD_wr_CMD;
s_icap_tmp <= CMD_wr_CMD;
when S13_DESYNC_CMD =>
s_icap_i <= DESYNC;
s_icap_tmp <= DESYNC;
when S14_NOOP =>
s_icap_i <= NOOP;
s_icap_tmp <= NOOP;
when S15_NOOP =>
s_icap_i <= NOOP;
s_icap_tmp <= NOOP;
when Q0_OK =>
null;
when others =>
......@@ -550,6 +565,14 @@ begin
when S12_CMD_CMD =>
s_multiboot_fsm <= S13_IPROG;
when S13_IPROG =>
s_multiboot_fsm <= S14_NOOP;
when S14_NOOP =>
s_multiboot_fsm <= S15_NOOP;
when S15_NOOP =>
s_multiboot_fsm <= S16_NOOP;
when S16_NOOP =>
s_multiboot_fsm <= S17_NOOP;
when S17_NOOP =>
s_multiboot_fsm <= Q0_OK;
when Q0_OK =>
s_multiboot_fsm <= R0_RESET;
......@@ -602,26 +625,20 @@ begin
case s_CTR0_core.OP is
when OP_FULLMULTIBOOT =>
update_wr_general(to_integer(s_CTR0_core.OP));
order_ICAP(v_MBA_slv(15 downto 0),
s_wr_ICAP_gen1);
order_ICAP(v_MBA_slv(31 downto 16),
s_wr_ICAP_gen2);
order_ICAP(v_GBA_slv(15 downto 0),
s_wr_ICAP_gen3);
order_ICAP(v_GBA_slv(31 downto 16),
s_wr_ICAP_gen4);
s_wr_ICAP_gen1 <= v_MBA_slv(15 downto 0);
s_wr_ICAP_gen2 <= v_MBA_slv(31 downto 16);
s_wr_ICAP_gen3 <= v_GBA_slv(15 downto 0);
s_wr_ICAP_gen4 <= v_GBA_slv(31 downto 16);
when OP_WR_MBA =>
update_wr_general(to_integer(s_CTR0_core.OP));
v_MBA_slv := f_STD_LOGIC_VECTOR(s_MBA);
order_ICAP(v_MBA_slv(15 downto 0),
s_wr_ICAP_gen1);
order_ICAP(v_MBA_slv(31 downto 16),
s_wr_ICAP_gen2);
s_wr_ICAP_gen1 <= v_MBA_slv(15 downto 0);
s_wr_ICAP_gen2 <= v_MBA_slv(31 downto 16);
when OP_WR_GBA =>
update_wr_general(to_integer(s_CTR0_core.OP));
v_GBA_slv := f_STD_LOGIC_VECTOR(s_GBA);
order_ICAP(v_GBA_slv(15 downto 0), s_wr_ICAP_gen3);
order_ICAP(v_GBA_slv(31 downto 16), s_wr_ICAP_gen4);
s_wr_ICAP_gen3 <= v_GBA_slv(15 downto 0);
s_wr_ICAP_gen4 <= v_GBA_slv(31 downto 16);
when OP_CMD_IPROG =>
update_wr_general(to_integer(s_CTR0_core.OP));
when others =>
......
hdl/multiboot/rtl/multiboot_regs.vhd
View file @ 29b287b7
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:53:14 02/20/2012
-- Design Name: multiboot module
-- Module Name: multiboot_regs - Behavioral
-- Project Name: CONV-TTL-BLO
-- Target Devices: Spartan 6 LX45T
-- Tool versions: ISE 13.3
-- Description:
--
-- Dependencies:
--
-- Revision Comment
-- 0.01 File created
-- 0.1 Added readbacks from ICAP interface
-- 0.2 Now there are two CTRL registers: CTR0 and CTR1
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
......
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