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C
Conv TTL Blocking - Gateware
Commit 26f027ea authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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User guide complete with FPGA logic information

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doc/ug-conv-ttl-blo.pdf
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doc/ug/Figures/pulse-gen-sigs.svg 0 → 100644
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doc/ug/ug-conv-ttl-blo.tex
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hdl/release/top/conv_ttl_blo_v2.vhd
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......@@ -406,7 +406,7 @@ begin
c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_RED when (rtmm_ok = '0') and (rtmp_ok = '0') else
bicolor_led_state(17 downto 16) <= c_LED_RED when (rtmm_ok = '0') and (rtmp_ok = '0') else
c_LED_OFF;
-- System power
......
hdl/reset_gen/rtl/reset_gen.vhd
View file @ 26f027ea
......@@ -43,7 +43,7 @@ entity reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 5_000_000
g_reset_time : positive := 12_000_000
);
port
(
......
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