Adding image with very basic functionality (triggers) and its debugging test.

0c44672d · gilsoriano · 01ed5238 · 0c44672d · 0c44672d
Commit 0c44672d authored Apr 04, 2012 by gilsoriano
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image0_top.vhd hdl/IMAGES/image0/rtl/image0_top.vhd +82 -0

image0_top_tb.vhd hdl/IMAGES/image0/test/image0_top_tb.vhd +107 -0

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--- a/hdl/IMAGES/image0/rtl/image0_top.vhd
+++ b/hdl/IMAGES/image0/rtl/image0_top.vhd
+----------------------------------------------------------------------------------
+-- Company:        CERN, BE-CO-HT
+-- Engineer:       Carlos Gil Soriano
+-- 
+-- Create Date:    16:55:00 04/04/2012 
+-- Design Name:    CONV_TTL_BLO image 0
+-- Module Name:    image0_top - Behavioral 
+-- Project Name:   CONV_TTL_BLO
+-- Target Devices: Spartan 6 SLX45T
+-- Tool versions: 
+-- Description:    image0_top.vhd comprises the integration of four vhdl modules:
+--                 1.- Trigger
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 1.00 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity image0_top is
+   generic(
+             g_NUMBER_OF_CHANNELS : INTEGER := 6
+          );
+   port(
+          rst_i        : in  STD_LOGIC;  
+          clk_i        : in  STD_LOGIC;      
+          pulse_i      : in  STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS - 1 downto 0);
+          pulse_o      : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS - 1 downto 0)
+       );
+end image0_top;
+
+architecture Behavioral of image0_top is
+
+   component trigger_top is
+      port (
+              pulse_i    : in  STD_LOGIC;
+              pulse_o    : out STD_LOGIC;
+              utc_i      : in  STD_LOGIC_VECTOR(95 downto 0);
+              wb_rst_i   : in  STD_LOGIC;		
+              wb_clk     : in  STD_LOGIC;		
+              wb_stb_i   : in  STD_LOGIC;
+              wb_cyc_i   : in  STD_LOGIC;
+              wb_ack_o   : out STD_LOGIC;
+              wb_err_o   : out STD_LOGIC;
+              wb_rty_o   : out STD_LOGIC;
+              wb_we_i    : in  STD_LOGIC;		
+              wb_sel_i   : in  STD_LOGIC_VECTOR(3  downto 0);
+              wb_data_i  : in  STD_LOGIC_VECTOR(31 downto 0);
+              wb_data_o  : out STD_LOGIC_VECTOR(31 downto 0);
+              wb_addr_i  : in  STD_LOGIC_VECTOR(2  downto 0)
+           );
+   end component;
+
+begin
+
+   trigger_channels_loop: for i in 0 to g_NUMBER_OF_CHANNELS - 1 generate
+   begin
+      trigger_inst: trigger_top
+      port map(
+                 pulse_i    => pulse_i(i), 
+                 pulse_o    => pulse_o(i), 
+                 utc_i      => (others => '0'), 
+                 wb_rst_i   => rst_i, 
+                 wb_clk     => clk_i, 
+                 wb_stb_i   => '0', 
+                 wb_cyc_i   => '0', 
+                 wb_ack_o   => 'Z', 
+                 wb_err_o   => 'Z', 
+                 wb_rty_o   => 'Z', 
+                 wb_we_i    => (others => '0'), 
+                 wb_sel_i   => (others => '0'), 
+                 wb_data_i  => (others => '0'), 
+                 wb_data_o  => (others => 'Z'), 
+              -- TODO: possibleslave_ to leave only one common wb_addr_s
+                 wb_addr_i  => (others => '0') 
+              );
+   end generate trigger_channels_loop;
+
+end Behavioral;
--- a/hdl/IMAGES/image0/test/image0_top_tb.vhd
+++ b/hdl/IMAGES/image0/test/image0_top_tb.vhd
+-- testbench template 
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALl;
+use IEEE.NUMERIC_STD.ALL;
+
+entity image0_top_tb is
+   end image0_top_tb;
+
+architecture Behavior of image0_top_tb is 
+
+   -- component declaration
+   component image0_top 
+      port(
+             rst_i   : in  STD_LOGIC;
+             clk_i   : in  STD_LOGIC;
+             pulse_i : in  STD_LOGIC_VECTOR(5 downto 0)
+             pulse_o : out STD_LOGIC_VECTOR(5 downto 0)
+          );
+   end component;
+
+   constant wb_clk_period : TIME = 50 ns;
+
+   signal rst_i           : STD_LOGIC;  
+   signal clk_i           : STD_LOGIC;  
+   signal pulse_i         : STD_LOGIC_VECTOR(5 downto 0); 
+   signal pulse_o         : STD_LOGIC_VECTOR(5 downto 0); 
+
+
+begin
+
+   -- component instantiation
+   image0_top_uut: image0_top
+   port map(
+              rst_i    =>  rst_i  , 
+              clk_i    =>  clk_i  ,
+              pulse_i  =>  pulse_i,
+              pulse_o  =>  pulse_o
+           );
+
+   wb_clk_proc: process
+   begin
+      clk_i <= '1';
+        wait for wb_clk_period;
+      clk_i <= '0';
+        wait for wb_clk_period;
+   end process;
+
+   tb_proc: process
+
+      procedure rst_sync(lenght: TIME)
+      begin
+          wait until rising_edge(clk_i);
+        rst_i  <= '1';
+          wait for 100000*wb_clk_period; -- 50ms
+        rst_i  <= '0';
+      end procedure;
+
+      procedure rst_async(t0: TIME; lenght: TIME)
+      begin
+      end procedure;
+
+      procedure pulse(channel: INTEGER; lenght:TIME)
+      begin
+           wait until rising_edge(wb_clk_i);
+         pulse_i(channel) <= '1';
+           wait for lenght;
+         pulse_i(channel) <= '0';
+      end procedure;
+
+   begin
+
+      rst_sync;
+
+
+      -------------------------------------------------------------------------
+      -- Pulse should be reproduced with a value of 1.5us which equals
+      -- 30 wb_ck_period clocks. Then, another pulse_lenght time slot, the
+      -- triggers will be forbidden to reproduce pulses for safety reasons.
+      -- A default current glitch mask of "111111" (six wb_clk_period, 300 ns)
+      -- is set.
+      --
+      --------------------------------
+      -- INPUT PULSES TESTS
+      --                           INPUT                 OUTPUT
+      -- 1.- Normal operation:      20 wb_clk_period      1 pulse
+      -- 2.- Testing antiglitch      5 wb_clk_period      0 pulses
+      -- 3.- Testing long pulses    59 wb_clk_period      1 pulse
+      --                            60 wb_clk_period      2 pulses?
+      --                            61 wb_clk_period      2 pulses
+      --------------------------------
+      -------------------------------------------------------------------------
+
+      pulse(1, 20 * wb_clk_period);
+        wait for 10 * wb_clk_period;
+      pulse(1,  5 * wb_clk_period);
+        wait for 10 * wb_clk_period;
+      pulse(1, 59 * wb_clk_period);
+        wait for 10 * wb_clk_period;
+      pulse(1, 60 * wb_clk_period);
+        wait for 10 * wb_clk_period;
+      pulse(1, 61 * wb_clk_period);
+        wait for 10 * wb_clk_period;
+
+   end process;
+
+end;