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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
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a7899fb2e20a069a10323c8ba1db5114c0b3fc7b
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conv-ttl-blo-gw
hdl
wr_core_demo
constraints
FPGAbank.ucf
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Stable version of the test of white rabbit. It works. Accessible via UART in extra header pins.
· 3f7fd876
gilsoriano
authored
Aug 21, 2012
3f7fd876
FPGAbank.ucf
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