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# Golden release gateware, version 0.0
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This firmware is the same as for the [v1.0 release
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gateware](release-1-0), except that the FWVERS field reads out as
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*0x00**. It is kept here for "historic" purposes.
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## Release notes
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- Pulse repetition with max. duty cycle of 1/5; input pulses with duty
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cycle \>1/5 are rejected
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- I2C to Wishbone bridge following the protocol defined together with
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ELMA
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- Dedicated CONV-TTL-BLO registers (see full memory map in the HDL
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guide):
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- Board ID register
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- CSR
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- remote logic reset
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- firmware version
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- state of on-board switches
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- state of [RTM detection
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lines](https://www.ohwr.org/pr\`ojects/conv-ttl-blo/wikis/RTM_board_detection)
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- state of I2C watchdog timer
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- Pulse and status LED control
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- [Remote
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reprogramming](/Xil-multiboot)
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## Binary file
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- [golden.bin](https://www.ohwr.org/2577)
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-- Binary file of raw golden
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bitstream
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- [golden-release.bin](https://www.ohwr.org/2579)
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-- Binary file containing golden bitstream and [gateware
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v1.0](release-1-0), downloaded by default to the flash of the first
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100 produced CONV-TTL-BLO
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## Sources
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- [golden branch in
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repository](https://www.ohwr.org/project/conv-ttl-blo-gw/tree/golden/)
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## Documentation
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- The block diagram of the logic is shown below.
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/2567
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\* For information on the implementation of each block, consult the HDL
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guide:
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git clone -b golden git:https://www.ohwr.org/level-conversion/conv-ttl-blo/conv-ttl-blo-gw.git
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cd doc/hdlguide/
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make
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-----
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Theodor-Adrian Stana, Jan. 2014
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