add initial top and subdirs README

5e38b491 · Antonin Broquet · 5e38b491 · 5e38b491 · 5e38b491
Commit 5e38b491 authored Sep 18, 2019 by Antonin Broquet
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README.md README.md +30 -0

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--- a/README.md
+++ b/README.md
+# CITY repository
+
+## Overview
+CITY board has been designed for the ESRF timing & synchronization system.
+It is a standalone pizza box form factor module.
+It is based on:
+- FASEC design: Zynq SoC with Processing System (PS) running Linux for control
+system interface, and Programmable Logic (PL) for application gateware.
+- FMC DAC 12b 1cha DDS: RF signal distribution over a White Rabbit network
+(RFoWR).
+
+This design is the next version of a previous module (WHIST) based on the SPEC
+card and implementing initial code of RFoWR (legacy WR Node Core, migrated to
+Mock Turtle).
+
+In order to be compatible with current ESRF WHIST system, CITY design gateware
+implements the legacy WR Node Core.
+It is in the roadmap to follow the current RFoWR implementation
+(with Mock Turtle and future RoE protocol).
+
+As this board has been developed for ESRF needs, it targets 352MHz RF frequency.
+500MHz frequency support (for other synchrotron) is considered.
+
+## Content
+circuit_board: PCB design
+
+hdl: VHDL source for application gateware (WR, RFoWR, programmable pulses and
+clocks...)
+
+
--- a/circuit_board/README.md
+++ b/circuit_board/README.md
+# PCB Design
+
+Circuit board for CITY application.
+Based on:
+- FASEC design,
+- FMC DAC 12b 1cha DDS
+
+## Contents
+CITY-V1-0: first version of PCB.
+
--- a/hdl/README.md
+++ b/hdl/README.md
+# HDL - Gateware
+
+Sources for application gateware.
+
+## Contents
+