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#### Q: An ASIC design is licensed under CERN-OHL-S or CERN-OHL-L. What are the implications regarding proprietary primitives and macros used in the design?
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This case is more complicated than the one for FPGA designs. We have not
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yet found good wording to make sure the primitive libraries (e.g. the
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so-called [PDKs](https://en.wikipedia.org/wikis/Process_design_kit) and
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[standard cell](https://en.wikipedia.org/wikis/Standard_cell) libraries)
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are excluded from the distribution obligations. Not excluding them would
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make the licences applicable in only an extremely reduced number of
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cases. Finding appropriate wording to make them qualify as "Available
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Components" is high in our
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agenda.
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Because of the way primitive libraries (e.g. the so-called
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[PDKs](https://en.wikipedia.org/wikis/Process_design_kit) and [standard
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cell](https://en.wikipedia.org/wikis/Standard_cell) libraries) are
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distributed in the ASIC design world, things are actually quite
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different from the FPGA case. Wording in CERN-OHL-S does not exclude
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these primitive libraries from the distribution obligations. Not
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excluding them makes the resulting licence applicable in only an
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extremely reduced number of cases now and in the short-term future:
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those where the PDKs and standard cells are released as Open Source
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Hardware. Those who would like a reciprocal licence which works with
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proprietary PDKs and standard cells should use CERN-OHL-L and not
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CERN-OHL-S.
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#### Q: Is an FPGA bitstream a Product according to the definition of Product in CERN OHL?
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