The Brazilian Synchrotron Light Laboratory (LNLS) is currently designing
a third-generation 3 GeV low emmitance synchrotron light source in
Campinas, Brazil, called Sirius, with commissioning due to 2018. The
main parameters of the machine are:
Injection energy (top up)
Natural bunch length
Circumference (storage ring)
For more information about the Sirius project please refer to this
In the context of the Sirius project, the Beam Diagnostics Group (DIG)
of LNLS has been called to develop a beam position monitoring system
(BPM) which must provide electron beam position real-time monitoring,
triggered data readouts, fast orbit feedback capabilities and advanced
beam diagnostics tools for the new accelerator’s injector and storage
ring. This project is primarily intended to deliver a BPM system for the
Sirius machine. Nevertheless, it is made open for the particle
accelerators community and general public for design reuse and
collaborative development, under the CERN Open Hardware
Licence and GPL-derived
The RF front-end is designed for button BPM pick-ups and must allow
nonlinearity lesser than 0.002 dB on top-up operation with maximum gain
of 60 dB. Bandpass filtering must provide 45 MHz, 80 dB bandwidth,
around the 500 MHz beam's main frequency (customizable for other beam
frequencies). 2x2 RF channel switching is used for non-linearity and
slow gain drifts compensation. Board temperature control is available to
minimize ambient temperature variations effects on position measurement
and RF channel health inspections.
The ADC board is a FPGA Mezzanine Card
(FMC) module fully compliant to the
ANSI/VITA 57.1 standard, providing 4-channel 16-bit 130 MS/s
(LTC2208IUP) or 250 MS/s (ISLA216P25) optimized for a 500 MHz center
frequency. Clocking can be phase-locked to external reference clock
(with fine frequency tune capability) or direct clock inputs (from front
panel or FMC clock) as well as bi-directional (configurable) trigger.
The DBE is a crate-based system which integrates in a single enclosure
the FPGA processing boards for beam position sensor data processing,
data acquisition and advanced diagnostics, fast orbit feedback (FOFB)
processing boards for feedback control algorithm processing, a dedicated
CPU for control system interface and RF front-ends control. The FPGA
boards are connected to the CPU via 4 lanes of PCIe Gen 2 link. The DBE
relies on the PICMG® MicroTCA R1.0 standard (MicroTCA.4), using COTS
crates and infrastructure boards such as MCH and CPU. Besides power,
cooling and IPMI infrastructure, the MicroTCA.4 backplane provides JTAG
chain access to all individual slots, GbE and PCIe switches, as well as
multigigabit point-to-point connectivity between slots, 8 M-LVDS
triggers, and 2 low-jitter radial clocks.
The FPGA board, a.k.a. AMC FMC Carrier (AFC), is fully compliant to
PICMG® AMC R2.0 standard (AMC.0, AMC.1, AMC.2) and features one Xilinx
Artix-7 200T FPGA device, 2 FMC high-pin count slots, 2 GB SDRAM (32-bit
interface), White Rabbit
support and standalone operation capability.
Start of project in OHR. Hardware designs will be done by external companies and LNLS.
Ask for quotations for RF front-end, ADC board and digital back-end designs.
DBE schematics started. Creotech is in charge of the boards design.