include/hw/*iface_regs.h: update reg map

Github commit lnls-dig/bpm-gw@d952234374 changed it.
So we update it here.

include/hw/wb_trigger_iface_regs.h

@@ -3,7 +3,7 @@
 
   * File           : wb_trigger_iface_regs.h
   * Author         : auto-generated by wbgen2 from wb_trigger_iface.wb
-  * Created        : Thu May 12 08:20:07 2016
+  * Created        : Fri May 20 13:37:27 2016
   * Standard       : ANSI C
 
     THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_trigger_iface.wb
@@ -36,11 +36,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 0 Control */
 #define WB_TRIG_IFACE_CH0_CTL_DIR             WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 0 Control */
+#define WB_TRIG_IFACE_CH0_CTL_DIR_POL         WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 0 Control */
-#define WB_TRIG_IFACE_CH0_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH0_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 0 Control */
-#define WB_TRIG_IFACE_CH0_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH0_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 0 Configuration Parameters */
 
@@ -75,11 +78,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 1 Control */
 #define WB_TRIG_IFACE_CH1_CTL_DIR             WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 1 Control */
+#define WB_TRIG_IFACE_CH1_CTL_DIR_POL         WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 1 Control */
-#define WB_TRIG_IFACE_CH1_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH1_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 1 Control */
-#define WB_TRIG_IFACE_CH1_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH1_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 1 Configuration Parameters */
 
@@ -114,11 +120,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 2 Control */
 #define WB_TRIG_IFACE_CH2_CTL_DIR             WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 2 Control */
+#define WB_TRIG_IFACE_CH2_CTL_DIR_POL         WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 2 Control */
-#define WB_TRIG_IFACE_CH2_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH2_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 2 Control */
-#define WB_TRIG_IFACE_CH2_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH2_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 2 Configuration Parameters */
 
@@ -153,11 +162,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 3 Control */
 #define WB_TRIG_IFACE_CH3_CTL_DIR             WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 3 Control */
+#define WB_TRIG_IFACE_CH3_CTL_DIR_POL         WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 3 Control */
-#define WB_TRIG_IFACE_CH3_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH3_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 3 Control */
-#define WB_TRIG_IFACE_CH3_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH3_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 3 Configuration Parameters */
 
@@ -192,11 +204,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 4 Control */
 #define WB_TRIG_IFACE_CH4_CTL_DIR             WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 4 Control */
+#define WB_TRIG_IFACE_CH4_CTL_DIR_POL         WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 4 Control */
-#define WB_TRIG_IFACE_CH4_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH4_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 4 Control */
-#define WB_TRIG_IFACE_CH4_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH4_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 4 Configuration Parameters */
 
@@ -231,11 +246,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 5 Control */
 #define WB_TRIG_IFACE_CH5_CTL_DIR             WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 5 Control */
+#define WB_TRIG_IFACE_CH5_CTL_DIR_POL         WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 5 Control */
-#define WB_TRIG_IFACE_CH5_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH5_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 5 Control */
-#define WB_TRIG_IFACE_CH5_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH5_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 5 Configuration Parameters */
 
@@ -270,11 +288,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 6 Control */
 #define WB_TRIG_IFACE_CH6_CTL_DIR             WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 6 Control */
+#define WB_TRIG_IFACE_CH6_CTL_DIR_POL         WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 6 Control */
-#define WB_TRIG_IFACE_CH6_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH6_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 6 Control */
-#define WB_TRIG_IFACE_CH6_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH6_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 6 Configuration Parameters */
 
@@ -309,11 +330,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 7 Control */
 #define WB_TRIG_IFACE_CH7_CTL_DIR             WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 7 Control */
+#define WB_TRIG_IFACE_CH7_CTL_DIR_POL         WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 7 Control */
-#define WB_TRIG_IFACE_CH7_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH7_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 7 Control */
-#define WB_TRIG_IFACE_CH7_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH7_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 7 Configuration Parameters */
 
@@ -348,11 +372,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 8 Control */
 #define WB_TRIG_IFACE_CH8_CTL_DIR             WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 8 Control */
+#define WB_TRIG_IFACE_CH8_CTL_DIR_POL         WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 8 Control */
-#define WB_TRIG_IFACE_CH8_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH8_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 8 Control */
-#define WB_TRIG_IFACE_CH8_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH8_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 8 Configuration Parameters */
 
@@ -387,11 +414,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 9 Control */
 #define WB_TRIG_IFACE_CH9_CTL_DIR             WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 9 Control */
+#define WB_TRIG_IFACE_CH9_CTL_DIR_POL         WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 9 Control */
-#define WB_TRIG_IFACE_CH9_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH9_CTL_RCV_COUNT_RST   WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 9 Control */
-#define WB_TRIG_IFACE_CH9_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH9_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 9 Configuration Parameters */
 
@@ -426,11 +456,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 10 Control */
 #define WB_TRIG_IFACE_CH10_CTL_DIR            WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 10 Control */
+#define WB_TRIG_IFACE_CH10_CTL_DIR_POL        WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 10 Control */
-#define WB_TRIG_IFACE_CH10_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH10_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 10 Control */
-#define WB_TRIG_IFACE_CH10_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH10_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 10 Configuration Parameters */
 
@@ -465,11 +498,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 11 Control */
 #define WB_TRIG_IFACE_CH11_CTL_DIR            WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 11 Control */
+#define WB_TRIG_IFACE_CH11_CTL_DIR_POL        WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 11 Control */
-#define WB_TRIG_IFACE_CH11_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH11_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 11 Control */
-#define WB_TRIG_IFACE_CH11_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH11_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 11 Configuration Parameters */
 
@@ -504,11 +540,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 12 Control */
 #define WB_TRIG_IFACE_CH12_CTL_DIR            WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 12 Control */
+#define WB_TRIG_IFACE_CH12_CTL_DIR_POL        WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 12 Control */
-#define WB_TRIG_IFACE_CH12_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH12_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 12 Control */
-#define WB_TRIG_IFACE_CH12_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH12_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 12 Configuration Parameters */
 
@@ -543,11 +582,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 13 Control */
 #define WB_TRIG_IFACE_CH13_CTL_DIR            WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 13 Control */
+#define WB_TRIG_IFACE_CH13_CTL_DIR_POL        WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 13 Control */
-#define WB_TRIG_IFACE_CH13_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH13_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 13 Control */
-#define WB_TRIG_IFACE_CH13_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH13_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 13 Configuration Parameters */
 
@@ -582,11 +624,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 14 Control */
 #define WB_TRIG_IFACE_CH14_CTL_DIR            WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 14 Control */
+#define WB_TRIG_IFACE_CH14_CTL_DIR_POL        WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 14 Control */
-#define WB_TRIG_IFACE_CH14_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH14_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 14 Control */
-#define WB_TRIG_IFACE_CH14_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH14_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 14 Configuration Parameters */
 
@@ -621,11 +666,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 15 Control */
 #define WB_TRIG_IFACE_CH15_CTL_DIR            WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 15 Control */
+#define WB_TRIG_IFACE_CH15_CTL_DIR_POL        WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 15 Control */
-#define WB_TRIG_IFACE_CH15_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH15_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 15 Control */
-#define WB_TRIG_IFACE_CH15_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH15_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 15 Configuration Parameters */
 
@@ -660,11 +708,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 16 Control */
 #define WB_TRIG_IFACE_CH16_CTL_DIR            WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 16 Control */
+#define WB_TRIG_IFACE_CH16_CTL_DIR_POL        WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 16 Control */
-#define WB_TRIG_IFACE_CH16_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH16_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 16 Control */
-#define WB_TRIG_IFACE_CH16_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH16_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 16 Configuration Parameters */
 
@@ -699,11 +750,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 17 Control */
 #define WB_TRIG_IFACE_CH17_CTL_DIR            WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 17 Control */
+#define WB_TRIG_IFACE_CH17_CTL_DIR_POL        WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 17 Control */
-#define WB_TRIG_IFACE_CH17_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH17_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 17 Control */
-#define WB_TRIG_IFACE_CH17_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH17_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 17 Configuration Parameters */
 
@@ -738,11 +792,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 18 Control */
 #define WB_TRIG_IFACE_CH18_CTL_DIR            WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 18 Control */
+#define WB_TRIG_IFACE_CH18_CTL_DIR_POL        WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 18 Control */
-#define WB_TRIG_IFACE_CH18_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH18_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 18 Control */
-#define WB_TRIG_IFACE_CH18_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH18_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 18 Configuration Parameters */
 
@@ -777,11 +834,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 19 Control */
 #define WB_TRIG_IFACE_CH19_CTL_DIR            WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 19 Control */
+#define WB_TRIG_IFACE_CH19_CTL_DIR_POL        WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 19 Control */
-#define WB_TRIG_IFACE_CH19_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH19_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 19 Control */
-#define WB_TRIG_IFACE_CH19_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH19_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 19 Configuration Parameters */
 
@@ -816,11 +876,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 20 Control */
 #define WB_TRIG_IFACE_CH20_CTL_DIR            WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 20 Control */
+#define WB_TRIG_IFACE_CH20_CTL_DIR_POL        WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 20 Control */
-#define WB_TRIG_IFACE_CH20_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH20_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 20 Control */
-#define WB_TRIG_IFACE_CH20_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH20_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 20 Configuration Parameters */
 
@@ -855,11 +918,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 21 Control */
 #define WB_TRIG_IFACE_CH21_CTL_DIR            WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 21 Control */
+#define WB_TRIG_IFACE_CH21_CTL_DIR_POL        WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 21 Control */
-#define WB_TRIG_IFACE_CH21_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH21_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 21 Control */
-#define WB_TRIG_IFACE_CH21_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH21_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 21 Configuration Parameters */
 
@@ -894,11 +960,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 22 Control */
 #define WB_TRIG_IFACE_CH22_CTL_DIR            WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 22 Control */
+#define WB_TRIG_IFACE_CH22_CTL_DIR_POL        WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 22 Control */
-#define WB_TRIG_IFACE_CH22_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH22_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 22 Control */
-#define WB_TRIG_IFACE_CH22_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH22_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 22 Configuration Parameters */
 
@@ -933,11 +1002,14 @@
 /* definitions for field: Trigger Direction in reg: Channel 23 Control */
 #define WB_TRIG_IFACE_CH23_CTL_DIR            WBGEN2_GEN_MASK(0, 1)
 
+/* definitions for field: Trigger Direction Polarity in reg: Channel 23 Control */
+#define WB_TRIG_IFACE_CH23_CTL_DIR_POL        WBGEN2_GEN_MASK(1, 1)
+
 /* definitions for field: Receiver Pulse Counter Reset in reg: Channel 23 Control */
-#define WB_TRIG_IFACE_CH23_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(1, 1)
+#define WB_TRIG_IFACE_CH23_CTL_RCV_COUNT_RST  WBGEN2_GEN_MASK(2, 1)
 
 /* definitions for field: Transmitter Pulse Counter Reset in reg: Channel 23 Control */
-#define WB_TRIG_IFACE_CH23_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(2, 1)
+#define WB_TRIG_IFACE_CH23_CTL_TRANSM_COUNT_RST WBGEN2_GEN_MASK(3, 1)
 
 /* definitions for register: Channel 23 Configuration Parameters */