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Beam Positoning Monitor - Gateware
Commit f70e34f3 authored by Lucas Russo's avatar Lucas Russo
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emb-sw/*: update fmc516 interface and communication

parent 20213a7b
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embedded-sw/dbe.vhd
View file @ f70e34f3
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embedded-sw/dbe_main.c
View file @ f70e34f3
......@@ -398,17 +398,17 @@ void fmc516_test()
i, fmc516_isla216_get_chipver(i));
}
for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
pp_printf("> FMC516_ISLA216_ADC%d test mode off\n", i);
fmc516_isla216_write_byte(ISLA216_OUT_TESTMODE(ISLA216_OUT_TESTIO_OFF),
ISLA216_TESTIO_REG, i);
}
//for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
// fmc516_isla216_test_ramp(i);
// pp_printf("> FMC516_ISLA216_ADC%d: ramp test enabled!\n", i);
// pp_printf("> FMC516_ISLA216_ADC%d test mode off\n", i);
// fmc516_isla216_write_byte(ISLA216_OUT_TESTMODE(ISLA216_OUT_TESTIO_OFF),
// ISLA216_TESTIO_REG, i);
//}
for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
fmc516_isla216_test_ramp(i);
pp_printf("> FMC516_ISLA216_ADC%d: ramp test enabled!\n", i);
}
//for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
// fmc516_isla216_test_midscale(i);
// pp_printf("> FMC516_ISLA216_ADC%d: test miscale enabled!\n", i);
......@@ -419,52 +419,52 @@ void fmc516_test()
fmc516_isla216_read_byte(ISLA216_TESTIO_REG, i));
}
pp_printf("> ADC data0 %d\n", fmc516_read_adc0(0));
pp_printf("> ADC data0 %d\n", fmc516_read_adc0(DEFAULT_FMC516_ID));
delay(LED_DELAY+32);
pp_printf("> ADC data0 %d\n", fmc516_read_adc0(0));
pp_printf("> ADC data0 %d\n", fmc516_read_adc0(DEFAULT_FMC516_ID));
delay(LED_DELAY+124);
pp_printf("> ADC data0 %d\n", fmc516_read_adc0(0));
pp_printf("> ADC data0 %d\n", fmc516_read_adc0(DEFAULT_FMC516_ID));
delay(LED_DELAY+1);
pp_printf("> ADC data0 %d\n", fmc516_read_adc0(0));
pp_printf("> ADC data0 %d\n", fmc516_read_adc0(DEFAULT_FMC516_ID));
delay(LED_DELAY);
pp_printf("> ADC data0 %d\n", fmc516_read_adc0(0));
pp_printf("> ADC data0 %d\n", fmc516_read_adc0(DEFAULT_FMC516_ID));
delay(LED_DELAY+12384);
pp_printf("> ADC data1 %d\n", fmc516_read_adc1(0));
pp_printf("> ADC data1 %d\n", fmc516_read_adc1(DEFAULT_FMC516_ID));
delay(LED_DELAY+32);
pp_printf("> ADC data1 %d\n", fmc516_read_adc1(0));
pp_printf("> ADC data1 %d\n", fmc516_read_adc1(DEFAULT_FMC516_ID));
delay(LED_DELAY+124);
pp_printf("> ADC data1 %d\n", fmc516_read_adc1(0));
pp_printf("> ADC data1 %d\n", fmc516_read_adc1(DEFAULT_FMC516_ID));
delay(LED_DELAY+1);
pp_printf("> ADC data1 %d\n", fmc516_read_adc1(0));
pp_printf("> ADC data1 %d\n", fmc516_read_adc1(DEFAULT_FMC516_ID));
delay(LED_DELAY);
pp_printf("> ADC data1 %d\n", fmc516_read_adc1(0));
pp_printf("> ADC data1 %d\n", fmc516_read_adc1(DEFAULT_FMC516_ID));
delay(LED_DELAY+12384);
pp_printf("> ADC data2 %d\n", fmc516_read_adc2(0));
pp_printf("> ADC data2 %d\n", fmc516_read_adc2(DEFAULT_FMC516_ID));
delay(LED_DELAY+32);
pp_printf("> ADC data2 %d\n", fmc516_read_adc2(0));
pp_printf("> ADC data2 %d\n", fmc516_read_adc2(DEFAULT_FMC516_ID));
delay(LED_DELAY+124);
pp_printf("> ADC data2 %d\n", fmc516_read_adc2(0));
pp_printf("> ADC data2 %d\n", fmc516_read_adc2(DEFAULT_FMC516_ID));
delay(LED_DELAY+1);
pp_printf("> ADC data2 %d\n", fmc516_read_adc2(0));
pp_printf("> ADC data2 %d\n", fmc516_read_adc2(DEFAULT_FMC516_ID));
delay(LED_DELAY);
pp_printf("> ADC data2 %d\n", fmc516_read_adc2(0));
delay(LED_DELAY+12384);
pp_printf("> ADC data2 %d\n", fmc516_read_adc2(DEFAULT_FMC516_ID));
delay(LED_DELAY+456);
pp_printf("> ADC data3 %d\n", fmc516_read_adc3(0));
pp_printf("> ADC data3 %d\n", fmc516_read_adc3(DEFAULT_FMC516_ID));
delay(LED_DELAY+32);
pp_printf("> ADC data3 %d\n", fmc516_read_adc3(0));
pp_printf("> ADC data3 %d\n", fmc516_read_adc3(DEFAULT_FMC516_ID));
delay(LED_DELAY+124);
pp_printf("> ADC data3 %d\n", fmc516_read_adc3(0));
pp_printf("> ADC data3 %d\n", fmc516_read_adc3(DEFAULT_FMC516_ID));
delay(LED_DELAY+1);
pp_printf("> ADC data3 %d\n", fmc516_read_adc3(0));
pp_printf("> ADC data3 %d\n", fmc516_read_adc3(DEFAULT_FMC516_ID));
delay(LED_DELAY);
pp_printf("> ADC data3 %d\n", fmc516_read_adc3(0));
delay(LED_DELAY+12384);
pp_printf("> ADC data3 %d\n", fmc516_read_adc3(DEFAULT_FMC516_ID));
delay(LED_DELAY+79);
dbg_print("> initilizing fmc516 delays\n");
fmc516_init_delays(0);
//dbg_print("> initilizing fmc516 delays\n");
fmc516_sweep_delays(DEFAULT_FMC516_ID);
pp_printf("> test finished...\n");
}
......
embedded-sw/dev/spi.c
View file @ f70e34f3
......@@ -136,11 +136,6 @@ int oc_spi_three_mode_rx(unsigned int id, int ss, int nbits, uint32_t *out)
// Write configuration to SPI core. SPI_CTRL_DIR = 0
spi[id]->CTRL = spi_config[id] | SPI_CTRL_CHAR_LEN(nbits);
spi[id]->SS = (1 << ss);
// TEST ONLY
spi[id]->RX0 = 0;
//spi[id]->RX1 = 0;
//spi[id]->RX2 = 0;
//spi[id]->RX3 = 0;
dbg_print("> spi[id]->TX0: 0x%8X\n", spi[id]->TX0);
dbg_print("> spi[id]->RX0: 0x%8X\n", spi[id]->RX0);
......
embedded-sw/fmc/fmc516/fmc516.c
View file @ f70e34f3
This diff is collapsed.
embedded-sw/fmc/fmc516/isla216p25.c
View file @ f70e34f3
......@@ -11,6 +11,7 @@
#include "spi.h" // SPI device functions
#include "isla216p25.h"
#include "isla216p25_regs.h"
#include "debug_print.h"
/*
* Which SPI ID is isla216p25? See board.h for definitions.
......@@ -83,17 +84,20 @@ void fmc516_isla216_write_instaddr(int addr, int length, int read, int ss)
fmc516_isla216_write_instaddr_raw(fmc516_isla216_reg, ss);
}
//ISLA216_CALSTATUS_REG
// word is 8-bit (1 byte) long for isla216p25
int fmc516_isla216_read_byte(int addr, int ss)
{
uint32_t val;
// TESTING! LENGTH MUST BE 1
fmc516_isla216_write_instaddr(addr, 1, 1, ss);
// Read the desired byte
fmc516_isla216_readw_raw(&val, ss);
dbg_print("fmc_read_byte: 0X%8X\n", val);
return val & 0xff;
}
......@@ -145,7 +149,8 @@ static void fmc516_isla216_load_regset(const struct default_dev_regs_t *regs, in
int i = 0;
while (regs[i].type != REGS_DEFAULT_END){
fmc516_isla216_write_byte(regs[i].val, regs[i].addr, ss);
if (regs[i].type == REGS_DEFAULT_INIT)
fmc516_isla216_write_byte(regs[i].val, regs[i].addr, ss);
++i;
}
}
......@@ -156,7 +161,7 @@ static void fmc516_isla216_load_regset(const struct default_dev_regs_t *regs, in
int fmc516_isla216_chkcal_stat(int ss)
{
return fmc516_isla216_read_byte(ISLA216_CALSTATUS_REG, ss) & ISLA216_CALDONE_MASK;
return fmc516_isla216_read_byte(ISLA216_CALSTATUS_REG, ss) & 0x01;
}
void fmc516_isla216_test_ramp(int ss)
......@@ -165,12 +170,18 @@ void fmc516_isla216_test_ramp(int ss)
ISLA216_TESTIO_REG, ss);
}
void fmc516_isla216_test_midscale(int ss)
{
fmc516_isla216_write_byte(ISLA216_OUT_TESTMODE(ISLA216_OUT_TESTIO_MIDSHORT),
ISLA216_TESTIO_REG, ss);
}
int fmc516_isla216_get_chipid(int ss)
{
return fmc516_isla216_read_byte(ISLA216_CHIPID_REG, ss) & ISLA216_CHIPID_MASK;
return fmc516_isla216_read_byte(ISLA216_CHIPID_REG, ss) & 0xff;
}
int fmc516_isla216_get_chipver(int ss)
{
return fmc516_isla216_read_byte(ISLA216_CHIPVER_REG, ss) & ISLA216_CHIPVER_MASK;
return fmc516_isla216_read_byte(ISLA216_CHIPVER_REG, ss) & 0xff;
}
embedded-sw/fmc/fmc516/lmk02000.c
View file @ f70e34f3
......@@ -49,7 +49,8 @@ static void fmc516_lmk02000_load_regset(const struct default_dev_regs_t *regs)
dbg_print("> fmc516_lmk02000_load_regset...\n");
while (regs[i].type != REGS_DEFAULT_END){
dbg_print("> fmc516_lmk02000_load_regset while: %d...\n", i);
fmc516_lmk02000_write_reg(regs[i].val);
if (regs[i].type == REGS_DEFAULT_INIT)
fmc516_lmk02000_write_reg(regs[i].val);
++i;
}
}
embedded-sw/include/fmc/fmc516/fmc516.h
View file @ f70e34f3
......@@ -22,5 +22,22 @@ int fmc516_exit(void);
// For now just ta few registers are initialized
void fmc516_init_regs(unsigned int id);
void fmc516_clk_sel(unsigned int id, int ext_clk);
void fmc516_led0(unsigned int id, int ext_clk);
void fmc516_led1(unsigned int id, int ext_clk);
void fmc516_led0(unsigned int id, int on);
void fmc516_led1(unsigned int id, int on);
void fmc516_reset_adcs(unsigned int id);
void fmc516_update_clk_dly(unsigned int id);
void fmc516_update_data_dly(unsigned int id);
/* Fix This! Code repetition! Fixed? */
void fmc516_adj_delay(unsigned int id, int ch, int clk_dly, int data_dly, int commit);
//void fmc516_adj_ch0_delay(unsigned int id, int clk_dly, int data_dly, int commit);
//void fmc516_adj_ch1_delay(unsigned int id, int clk_dly, int data_dly, int commit);
//void fmc516_adj_ch2_delay(unsigned int id, int clk_dly, int data_dly, int commit);
//void fmc516_adj_ch3_delay(unsigned int id, int clk_dly, int data_dly, int commit);
void fmc516_sweep_delays(unsigned int id);
uint32_t fmc516_read_adc0(unsigned int id);
uint32_t fmc516_read_adc1(unsigned int id);
uint32_t fmc516_read_adc2(unsigned int id);
uint32_t fmc516_read_adc3(unsigned int id);
embedded-sw/include/fmc/fmc516/isla216p25.h
View file @ f70e34f3
......@@ -12,26 +12,31 @@
#include "regs.h"
#define FMC516_ISLA216_ADC0 0
#define FMC516_ISLA216_SS_ADC0 ((1 << 0) & 0xff)
#define FMC516_ISLA216_ADC1 1
#define FMC516_ISLA216_SS_ADC1 ((1 << 1) & 0xff)
#define FMC516_ISLA216_ADC2 2
#define FMC516_ISLA216_SS_ADC2 ((1 << 2) & 0xff)
#define FMC516_ISLA216_ADC3 3
#define FMC516_ISLA216_SS_ADC3 ((1 << 3) & 0xff)
#define FMC516_NUM_ISLA216 4
#define FMC516_ISLA216_RW_SIZE 1
#define FMC516_ISLA216_RW_OFS 0
#define FMC516_ISLA216_RW_MASK 0x1
#define FMC516_ISLA216_RW_OFS 15
#define FMC516_ISLA216_RW_MASK 0x8000
#define FMC516_ISLA216_RW(x) (((x) << FMC516_ISLA216_RW_OFS) & FMC516_ISLA216_RW_MASK)
#define FMC516_ISLA216_READ (FMC516_ISLA216_RW(1))
//#define FMC516_ISLA216_WRITE (~FMC516_ISLA216_READ)
#define FMC516_ISLA216_LENGTH_SIZE 2
#define FMC516_ISLA216_LENGTH_OFS 1
#define FMC516_ISLA216_LENGTH_MASK 0x6
#define FMC516_ISLA216_LENGTH_OFS 13
#define FMC516_ISLA216_LENGTH_MASK 0x6000
#define FMC516_ISLA216_LENGTH(x) (((x) << FMC516_ISLA216_LENGTH_OFS) & FMC516_ISLA216_LENGTH_MASK)
#define FMC516_ISLA216_ADDR_SIZE 13
#define FMC516_ISLA216_ADDR_OFS 3
#define FMC516_ISLA216_ADDR_MASK 0xFFF8
#define FMC516_ISLA216_ADDR_OFS 0
#define FMC516_ISLA216_ADDR_MASK 0x1FFF
#define FMC516_ISLA216_ADDR(x) (((x) << FMC516_ISLA216_ADDR_OFS) & FMC516_ISLA216_ADDR_MASK)
#define FMC516_ISLA216_INSTADDR_SIZE (FMC516_ISLA216_RW_SIZE + \
......
embedded-sw/include/fmc/fmc516/lmk02000_regs.h
View file @ f70e34f3
......@@ -38,3 +38,10 @@ const struct default_dev_regs_t lmk02000_regs_default[] =
{REGS_DEFAULT_NO_INIT, 4, 0xf, 0x4003e800|15 },
{REGS_DEFAULT_END, 0, 0 , 0 }
};
//const struct default_dev_regs_t lmk02000_regs_default[] =
//{
// // Power down LMK02000 (1<<26)
// {REGS_DEFAULT_INIT, 4, 0xe, (1<<26)|14 },
// {REGS_DEFAULT_END, 0, 0 , 0 }
//};
embedded-sw/include/hw/wb_fmc516.h
View file @ f70e34f3
......@@ -3,7 +3,7 @@
* File : fmc516_regs.h
* Author : auto-generated by wbgen2 from wb_fmc516_regs.wb
* Created : Sat Dec 8 14:13:16 2012
* Created : Sat Mar 16 13:03:57 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc516_regs.wb
......@@ -122,20 +122,23 @@
/* definitions for register: Global ADC Control register */
/* definitions for field: Reset/Update ADC clock/data chains delay in reg: Global ADC Control register */
#define FMC516_ADC_CTL_UPDATE_DLY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Reset/Update ADC clock chains delay in reg: Global ADC Control register */
#define FMC516_ADC_CTL_UPDATE_CLK_DLY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Reset/Update ADC data chains delay in reg: Global ADC Control register */
#define FMC516_ADC_CTL_UPDATE_DATA_DLY WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reset ADCs in reg: Global ADC Control register */
#define FMC516_ADC_CTL_RST_ADCS WBGEN2_GEN_MASK(1, 1)
#define FMC516_ADC_CTL_RST_ADCS WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reset Div ADCs in reg: Global ADC Control register */
#define FMC516_ADC_CTL_RST_DIV_ADCS WBGEN2_GEN_MASK(2, 1)
#define FMC516_ADC_CTL_RST_DIV_ADCS WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Global ADC Control register */
#define FMC516_ADC_CTL_RESERVED_MASK WBGEN2_GEN_MASK(3, 29)
#define FMC516_ADC_CTL_RESERVED_SHIFT 3
#define FMC516_ADC_CTL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define FMC516_ADC_CTL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
#define FMC516_ADC_CTL_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define FMC516_ADC_CTL_RESERVED_SHIFT 4
#define FMC516_ADC_CTL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define FMC516_ADC_CTL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Channel 0 status register */
......@@ -201,6 +204,20 @@
#define FMC516_CH0_CTL_RESERVED_DATA_INCDEC_DLY_W(value) WBGEN2_GEN_WRITE(value, 26, 6)
#define FMC516_CH0_CTL_RESERVED_DATA_INCDEC_DLY_R(reg) WBGEN2_GEN_READ(reg, 26, 6)
/* definitions for register: Channel 0 delay control register */
/* definitions for field: Falling edge data delay in reg: Channel 0 delay control register */
#define FMC516_CH0_DLY_CTL_FE_DLY_MASK WBGEN2_GEN_MASK(0, 2)
#define FMC516_CH0_DLY_CTL_FE_DLY_SHIFT 0
#define FMC516_CH0_DLY_CTL_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define FMC516_CH0_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 0 delay control register */
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
/* definitions for register: Channel 1 status register */
/* definitions for field: Channel 1 current ADC value in reg: Channel 1 status register */
......@@ -265,6 +282,20 @@
#define FMC516_CH1_CTL_RESERVED_DATA_INCDEC_DLY_W(value) WBGEN2_GEN_WRITE(value, 26, 6)
#define FMC516_CH1_CTL_RESERVED_DATA_INCDEC_DLY_R(reg) WBGEN2_GEN_READ(reg, 26, 6)
/* definitions for register: Channel 1 delay control register */
/* definitions for field: Falling edge data delay in reg: Channel 1 delay control register */
#define FMC516_CH1_DLY_CTL_FE_DLY_MASK WBGEN2_GEN_MASK(0, 2)
#define FMC516_CH1_DLY_CTL_FE_DLY_SHIFT 0
#define FMC516_CH1_DLY_CTL_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define FMC516_CH1_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 1 delay control register */
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
/* definitions for register: Channel 2 status register */
/* definitions for field: Channel 2 current ADC value in reg: Channel 2 status register */
......@@ -329,6 +360,20 @@
#define FMC516_CH2_CTL_RESERVED_DATA_INCDEC_DLY_W(value) WBGEN2_GEN_WRITE(value, 26, 6)
#define FMC516_CH2_CTL_RESERVED_DATA_INCDEC_DLY_R(reg) WBGEN2_GEN_READ(reg, 26, 6)
/* definitions for register: Channel 2 delay control register */
/* definitions for field: Falling edge data delay in reg: Channel 2 delay control register */
#define FMC516_CH2_DLY_CTL_FE_DLY_MASK WBGEN2_GEN_MASK(0, 2)
#define FMC516_CH2_DLY_CTL_FE_DLY_SHIFT 0
#define FMC516_CH2_DLY_CTL_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define FMC516_CH2_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 2 delay control register */
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
/* definitions for register: Channel 3 status register */
/* definitions for field: Channel 3 current ADC value in reg: Channel 3 status register */
......@@ -393,6 +438,20 @@
#define FMC516_CH3_CTL_RESERVED_DATA_INCDEC_DLY_W(value) WBGEN2_GEN_WRITE(value, 26, 6)
#define FMC516_CH3_CTL_RESERVED_DATA_INCDEC_DLY_R(reg) WBGEN2_GEN_READ(reg, 26, 6)
/* definitions for register: Channel 3 delay control register */
/* definitions for field: Falling edge data delay in reg: Channel 3 delay control register */
#define FMC516_CH3_DLY_CTL_FE_DLY_MASK WBGEN2_GEN_MASK(0, 2)
#define FMC516_CH3_DLY_CTL_FE_DLY_SHIFT 0
#define FMC516_CH3_DLY_CTL_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define FMC516_CH3_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 3 delay control register */
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
PACKED struct FMC516_WB {
/* [0x0]: REG Status register */
uint32_t FMC_STA;
......@@ -408,18 +467,26 @@ PACKED struct FMC516_WB {
uint32_t CH0_STA;
/* [0x18]: REG Channel 0 control register */
uint32_t CH0_CTL;
/* [0x1c]: REG Channel 1 status register */
/* [0x1c]: REG Channel 0 delay control register */
uint32_t CH0_DLY_CTL;
/* [0x20]: REG Channel 1 status register */
uint32_t CH1_STA;
/* [0x20]: REG Channel 1 control register */
/* [0x24]: REG Channel 1 control register */
uint32_t CH1_CTL;
/* [0x24]: REG Channel 2 status register */
/* [0x28]: REG Channel 1 delay control register */
uint32_t CH1_DLY_CTL;
/* [0x2c]: REG Channel 2 status register */
uint32_t CH2_STA;
/* [0x28]: REG Channel 2 control register */
/* [0x30]: REG Channel 2 control register */
uint32_t CH2_CTL;
/* [0x2c]: REG Channel 3 status register */
/* [0x34]: REG Channel 2 delay control register */
uint32_t CH2_DLY_CTL;
/* [0x38]: REG Channel 3 status register */
uint32_t CH3_STA;
/* [0x30]: REG Channel 3 control register */
/* [0x3c]: REG Channel 3 control register */
uint32_t CH3_CTL;
/* [0x40]: REG Channel 3 delay control register */
uint32_t CH3_DLY_CTL;
};
#endif
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