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Beam Positoning Monitor - Gateware
Commit f2cb30f4 authored by Lucas Russo's avatar Lucas Russo
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emb-sw/*: simple fixes reallocation of files

parent c632744b
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Showing with 532 additions and 497 deletions
embedded-sw/Makefile
View file @ f2cb30f4
......@@ -9,6 +9,8 @@ CONFIG_PPRINTF =? 1
#endif
CONFIG_ETHERBONE =? 1
CONFIG_FMC150 ?= 1
CONFIG_FMC516 ?= 1
# and don't touch the rest unless you know what you're doing.
CROSS_COMPILE ?= lm32-elf-
......@@ -26,6 +28,8 @@ OBJS_DBE = dbe_main.o
INCLUDE_DIRS = -Iinclude \
-Iinclude/memmgr \
-Iinclude/fmc/fmc150 \
-Iinclude/fmc/fmc516 \
-I$(CURDIR)/pp_printf \
-I$(CURDIR)/lib \
-I$(CURDIR)/lib/ethmac
......@@ -49,6 +53,7 @@ include lib/lib.mk
include dev/dev.mk
include pp_printf/printf.mk
include boards/boards.mk
include fmc/fmc.mk
CFLAGS += $(CFLAGS_PLATFORM) $(CFLAGS_EB) $(INCLUDE_DIRS) \
$(CFLAGS_MEMMGR) $(CFLAGS_DEBUG) -ffunction-sections -fdata-sections \
......@@ -59,7 +64,7 @@ LDFLAGS = $(LDFLAGS_PLATFORM) \
OBJS = $(OBJS_PLATFORM) $(OBJS_DBE) \
$(OBJS_SHELL) $(OBJS_TESTS) $(OBJS_LIB) \
$(OBJS_DEV) $(OBJS_BOARD)
$(OBJS_DEV) $(OBJS_BOARD) $(OBJS_FMC)
OUTPUT = dbe
#OUTPUT = dbe_test
......
embedded-sw/dev/dev.mk
View file @ f2cb30f4
OBJS_DEV = dev/dma.o \
dev/fmc150.o \
dev/gpio.o \
dev/uart.o \
dev/sdb.o \
dev/ethmac_adapt.o \
dev/spi.o
dev/spi.o \
dev/i2c.o \
dev/onewire.o
embedded-sw/dev/dma.c
View file @ f2cb30f4
......@@ -7,48 +7,48 @@ dma_t **dma;
int dma_init(void)
{
int i;
struct dev_node *dev_p = 0;
int i;
struct dev_node *dev_p = 0;
if (!dma_devl->devices)
return -1;
if (!dma_devl->devices)
return -1;
// get all base addresses
dma = (dma_t **) memmgr_alloc(sizeof(dma_t *)*dma_devl->size);
// get all base addresses
dma = (dma_t **) memmgr_alloc(sizeof(dma_t *)*dma_devl->size);
//dbg_print("> dma size: %d\n", dma_devl->size);
//dbg_print("> dma size: %d\n", dma_devl->size);
for (i = 0, dev_p = dma_devl->devices; i < dma_devl->size;
++i, dev_p = dev_p->next) {
dma[i] = (dma_t *) dev_p->base;
//dbg_print("> dma addr[%d]: %08X\n", i, gpio[i]);
}
//dma = (dma_t *)dma_devl->devices->base;//BASE_GPIO;
return 0;
for (i = 0, dev_p = dma_devl->devices; i < dma_devl->size;
++i, dev_p = dev_p->next) {
dma[i] = (dma_t *) dev_p->base;
//dbg_print("> dma addr[%d]: %08X\n", i, gpio[i]);
}
//dma = (dma_t *)dma_devl->devices->base;//BASE_GPIO;
return 0;
}
/* DMA user interface definition */
int read_is_addr(unsigned int id)
{
return dma[id]->RD_ADDR;
return dma[id]->RD_ADDR;
}
void write_is_addr(unsigned int id, int addr)
{
dma[id]->WR_ADDR = (uint32_t)addr;
dma[id]->WR_ADDR = (uint32_t)addr;
}
int read_strd(unsigned int id)
{
return dma[id]->RD_STRD;
return dma[id]->RD_STRD;
}
void write_strd(unsigned int id, int strd)
{
dma[id]->WR_STRD = (uint32_t) strd;
dma[id]->WR_STRD = (uint32_t) strd;
}
int read_tr_count(unsigned int id)
{
return dma[id]->TR_COUNT;
return dma[id]->TR_COUNT;
}
embedded-sw/dev/ethmac_adapt.c
View file @ f2cb30f4
......@@ -9,47 +9,47 @@ ethmac_adapt_t **ethmac_adapt;
int ethmac_adapt_init(void)
{
int i;
struct dev_node *dev_p = 0;
int i;
struct dev_node *dev_p = 0;
if (!ethmac_adapt_devl->devices)
return -1;
if (!ethmac_adapt_devl->devices)
return -1;
// get all base addresses
ethmac_adapt = (ethmac_adapt_t **) memmgr_alloc(sizeof(ethmac_adapt_t *)*ethmac_adapt_devl->size);
// get all base addresses
ethmac_adapt = (ethmac_adapt_t **) memmgr_alloc(sizeof(ethmac_adapt_t *)*ethmac_adapt_devl->size);
//dbg_print("> ethmac_adapt size: %d\n", ethmac_adapt_devl->size);
//dbg_print("> ethmac_adapt size: %d\n", ethmac_adapt_devl->size);
for (i = 0, dev_p = ethmac_adapt_devl->devices; i < ethmac_adapt_devl->size;
++i, dev_p = dev_p->next) {
ethmac_adapt[i] = (ethmac_adapt_t *) dev_p->base;
//dbg_print("> dma addr[%d]: %08X\n", i, gpio[i]);
}
//ethmac_adapt = (ethmac_adapt_t *)ethmac_adapt_devl->devices->base;//BASE_GPIO;
return 0;
for (i = 0, dev_p = ethmac_adapt_devl->devices; i < ethmac_adapt_devl->size;
++i, dev_p = dev_p->next) {
ethmac_adapt[i] = (ethmac_adapt_t *) dev_p->base;
//dbg_print("> dma addr[%d]: %08X\n", i, gpio[i]);
}
//ethmac_adapt = (ethmac_adapt_t *)ethmac_adapt_devl->devices->base;//BASE_GPIO;
return 0;
}
int ethmac_adapt_set_base(unsigned int id, unsigned int base_rx, unsigned int base_tx)
{
ethmac_adapt[id]->base_rx = base_rx;
ethmac_adapt[id]->base_tx = base_tx;
ethmac_adapt[id]->base_rx = base_rx;
ethmac_adapt[id]->base_tx = base_tx;
return 0;
return 0;
}
int ethmac_adapt_set_length(unsigned int id, unsigned int length)
{
ethmac_adapt[id]->length = length;
ethmac_adapt[id]->length = length;
return 0;
return 0;
}
int ethmac_adapt_go(unsigned int id)
{
// write anything to trigger a transaction
ethmac_adapt[id]->doit = 1;
// write anything to trigger a transaction
ethmac_adapt[id]->doit = 1;
return 0;
return 0;
}
......
embedded-sw/dev/gpio.c
View file @ f2cb30f4
......@@ -7,52 +7,52 @@ gpio_t **gpio;
int gpio_init()
{
int i;
struct dev_node *dev_p = 0;
int i;
struct dev_node *dev_p = 0;
if (!gpio_devl->devices)
return -1;
if (!gpio_devl->devices)
return -1;
// get all base addresses
gpio = (gpio_t **) memmgr_alloc(sizeof(gpio_t *)*gpio_devl->size);
// get all base addresses
gpio = (gpio_t **) memmgr_alloc(sizeof(gpio_t *)*gpio_devl->size);
//dbg_print("> gpio size: %d\n", gpio_devl->size);
//dbg_print("> gpio size: %d\n", gpio_devl->size);
for (i = 0, dev_p = gpio_devl->devices; i < gpio_devl->size;
++i, dev_p = dev_p->next) {
gpio[i] = (gpio_t *) dev_p->base;
//dbg_print("> gpio addr[%d]: %08X\n", i, gpio[i]);
}
//gpio = (gpio_t *)gpio_devl->devices->base;//BASE_GPIO;
return 0;
for (i = 0, dev_p = gpio_devl->devices; i < gpio_devl->size;
++i, dev_p = dev_p->next) {
gpio[i] = (gpio_t *) dev_p->base;
//dbg_print("> gpio addr[%d]: %08X\n", i, gpio[i]);
}
//gpio = (gpio_t *)gpio_devl->devices->base;//BASE_GPIO;
return 0;
}
int gpio_exit()
{
// free gpio structure
memmgr_free(gpio);
// free gpio structure
memmgr_free(gpio);
return 0;
return 0;
}
/* GPIO user interface definition */
void gpio_out(unsigned int id, int pin, int val)
{
if(val)
gpio[id]->SODR = (1<<pin);
else
gpio[id]->CODR = (1<<pin);
if(val)
gpio[id]->SODR = (1<<pin);
else
gpio[id]->CODR = (1<<pin);
}
void gpio_dir(unsigned int id, int pin, int val)
{
if(val)
gpio[id]->DDR |= (1<<pin);
else
gpio[id]->DDR &= ~(1<<pin);
if(val)
gpio[id]->DDR |= (1<<pin);
else
gpio[id]->DDR &= ~(1<<pin);
}
int gpio_in(unsigned int id, int pin)
{
return gpio[id]->PSR & (1<<pin) ? 1 : 0;
return gpio[id]->PSR & (1<<pin) ? 1 : 0;
}
embedded-sw/dev/uart.c
View file @ f2cb30f4
......@@ -4,54 +4,54 @@
#include "uart.h" // UART device functions
#define CALC_BAUD(baudrate) \
( ((( (unsigned long long)baudrate * 8ULL) << (16 - 7)) + \
(CPU_CLOCK >> 8)) / (CPU_CLOCK >> 7) )
( ((( (unsigned long long)baudrate * 8ULL) << (16 - 7)) + \
(CPU_CLOCK >> 8)) / (CPU_CLOCK >> 7) )
// Global UART handler.
uart_t **uart;
int uart_init(void)
{
int i;
struct dev_node *dev_p = 0;
int i;
struct dev_node *dev_p = 0;
if (!uart_devl->devices)
return -1;
if (!uart_devl->devices)
return -1;
// get all base addresses
uart = (uart_t **) memmgr_alloc(sizeof(uart_t *)*uart_devl->size);
// get all base addresses
uart = (uart_t **) memmgr_alloc(sizeof(uart_t *)*uart_devl->size);
//dbg_print("> uart size: %d\n", uart_devl->size);
//dbg_print("> uart size: %d\n", uart_devl->size);
for (i = 0, dev_p = uart_devl->devices; i < uart_devl->size;
++i, dev_p = dev_p->next) {
uart[i] = (uart_t *) dev_p->base;
uart[i]->BCR = CALC_BAUD(UART_BAUDRATE);
//dbg_print("> uart addr[%d]: %08X\n", i, gpio[i]);
}
//uart = (uart_t *)uart_devl->devices->base;//BASE_GPIO;
return 0;
for (i = 0, dev_p = uart_devl->devices; i < uart_devl->size;
++i, dev_p = dev_p->next) {
uart[i] = (uart_t *) dev_p->base;
uart[i]->BCR = CALC_BAUD(UART_BAUDRATE);
//dbg_print("> uart addr[%d]: %08X\n", i, gpio[i]);
}
//uart = (uart_t *)uart_devl->devices->base;//BASE_GPIO;
return 0;
}
void uart_write_byte(unsigned int id, int b)
{
if (b == '\n')
uart_write_byte(id, '\r');
while (uart[id]->SR & UART_SR_TX_BUSY) ;
uart[id]->TDR = b;
if (b == '\n')
uart_write_byte(id, '\r');
while (uart[id]->SR & UART_SR_TX_BUSY) ;
uart[id]->TDR = b;
}
void uart_write_string(unsigned int id, char *s)
{
while (*s)
uart_write_byte(id, *(s++));
while (*s)
uart_write_byte(id, *(s++));
}
// Only for use with puts
void uart_default_write_string(char *s)
{
while (*s)
uart_write_byte(DEFAULT_UART, *(s++));
while (*s)
uart_write_byte(DEFAULT_UART, *(s++));
}
// See http://gcc.gnu.org/onlinedocs/gcc/Function-Attributes.html
......@@ -60,13 +60,13 @@ int puts(const char *s) __attribute__((alias("uart_default_write_string")));
int uart_poll(unsigned int id)
{
return uart[id]->SR & UART_SR_RX_RDY;
return uart[id]->SR & UART_SR_RX_RDY;
}
int uart_read_byte(unsigned int id)
{
if (!uart_poll(id))
return -1;
if (!uart_poll(id))
return -1;
return uart[id]->RDR & 0xff;
return uart[id]->RDR & 0xff;
}
embedded-sw/include/dma.h
View file @ f2cb30f4
......@@ -4,16 +4,16 @@
#include "inttypes.h"
/*
This structure must conform to what it is specified in the
FPGA software-acessible registers. See general-cores/cores/wishbone/wb_dma.vhd
This structure must conform to what it is specified in the
FPGA software-acessible registers. See general-cores/cores/wishbone/wb_dma.vhd
*/
struct DMA_WB
{
uint32_t RD_ADDR; /* Read issue address register */
uint32_t WR_ADDR; /* Write issue address register */
uint32_t RD_STRD; /* Read stride */
uint32_t WR_STRD; /* Write stride */
uint32_t TR_COUNT; /* Transfer count */
uint32_t RD_ADDR; /* Read issue address register */
uint32_t WR_ADDR; /* Write issue address register */
uint32_t RD_STRD; /* Read stride */
uint32_t WR_STRD; /* Write stride */
uint32_t TR_COUNT; /* Transfer count */
};
typedef volatile struct DMA_WB dma_t;
......
embedded-sw/include/ethmac_adapt.h
View file @ f2cb30f4
......@@ -4,10 +4,10 @@
#include "inttypes.h"
struct ETHMAC_ADAPT {
uint32_t doit;
uint32_t base_tx;
uint32_t base_rx;
uint32_t length;
uint32_t doit;
uint32_t base_tx;
uint32_t base_rx;
uint32_t length;
};
typedef volatile struct ETHMAC_ADAPT ethmac_adapt_t;
......
embedded-sw/include/gpio.h
View file @ f2cb30f4
......@@ -4,15 +4,15 @@
#include "inttypes.h"
/*
This structure must conform to what it is specified in the
FPGA software-acessible registers. See general-cores/cores/wishbone/wb_gpio_port.vhd
This structure must conform to what it is specified in the
FPGA software-acessible registers. See general-cores/cores/wishbone/wb_gpio_port.vhd
*/
struct GPIO_WB
{
uint32_t CODR; /* Clear output register */
uint32_t SODR; /* Set output register */
uint32_t DDR; /* Data direction register (1 means out) */
uint32_t PSR; /* Pin state register */
uint32_t CODR; /* Clear output register */
uint32_t SODR; /* Set output register */
uint32_t DDR; /* Data direction register (1 means out) */
uint32_t PSR; /* Pin state register */
};
typedef volatile struct GPIO_WB gpio_t;
......
embedded-sw/include/hw/wb_fmc150.h
View file @ f2cb30f4
/*
Register definitions for slave core: FMC ADC/DAC interface registers
Register definitions for slave core: FMC ADC/DAC interface registers
* File : wb_fmc150.h
* Author : auto-generated by wbgen2 from xfmc150.wb
......
embedded-sw/include/hw/wb_uart.h
View file @ f2cb30f4
/*
Register definitions for slave core: Simple Wishbone UART
Register definitions for slave core: Simple Wishbone UART
* File : ../../../../software/include/hw/wb_uart.h
* Author : auto-generated by wbgen2 from uart.wb
......
embedded-sw/include/hw/wb_vuart.h
View file @ f2cb30f4
/*
Register definitions for slave core: Virtual UART
Register definitions for slave core: Virtual UART
* File : wb_vuart.h
* Author : auto-generated by wbgen2 from wb_virtual_uart.wb
......
embedded-sw/lib/debug_print.c
View file @ f2cb30f4
......@@ -3,19 +3,19 @@
void debug_print(const char *fmt, ...)
{
va_list l;
va_list l;
va_start(l, fmt);
pp_printf(fmt, l);
va_end(l);
va_start(l, fmt);
pp_printf(fmt, l);
va_end(l);
}
void debug_print2(const char *fmt, const char *data, int len)
{
int i;
int i;
for (i = 0; i < len; ++i)
pp_printf(fmt, data[i]);
for (i = 0; i < len; ++i)
pp_printf(fmt, data[i]);
pp_printf("\n");
pp_printf("\n");
}
embedded-sw/lib/debug_print.h 0 → 100644
View file @ f2cb30f4
/*
* Copyright (C) 2012 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#ifndef _DEBUG_PRINT_
#define _DEBUG_PRINT_
#include <stdarg.h>
#include "pp-printf.h"
void debug_print(const char *fmt, ...);
//__attribute__((format(printf,1,2)));
void debug_print2(const char *fmt, const char *data, int len);
#ifdef DEBUG_PRINT
#define dbg_print(fmt, ...) \
pp_printf("%s (%d): "fmt, __FILE__, __LINE__, ##__VA_ARGS__)
#define dbg_print2(fmt, data, len) \
debug_print2(fmt, data, len)
#else
#define dbg_print(...)
#define dbg_print2(fmt, data, len)
#endif
#endif
embedded-sw/lib/ethmac/ethmac-int.c
View file @ f2cb30f4
......@@ -5,100 +5,100 @@
static void oeth_rx(void)
{
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
volatile oeth_bd *rx_bdp;
int pkt_len, i;
int bad = 0;
dbg_print("oeth_rx:\n");
rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
/* Find RX buffers marked as having received data */
for(i = 0; i < OETH_RXBD_NUM; i++)
{
dbg_print("> rxbd_num: %d\n", i);
bad=0;
/* Looking for buffer descriptors marked not empty */
if(!(rx_bdp[i].len_status & OETH_RX_BD_EMPTY)){
/* Check status for errors.
*/
dbg_print("> len_status: 0X%8X\n", rx_bdp[i].len_status);
if (rx_bdp[i].len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT)) {
bad = 1;
dbg_print("> short!\n");
}
if (rx_bdp[i].len_status & OETH_RX_BD_DRIBBLE) {
bad = 1;
dbg_print("> dribble!\n");
}
if (rx_bdp[i].len_status & OETH_RX_BD_CRCERR) {
bad = 1;
dbg_print("> CRC error!\n");
}
if (rx_bdp[i].len_status & OETH_RX_BD_OVERRUN) {
bad = 1;
dbg_print("> overrun!\n");
}
if (rx_bdp[i].len_status & OETH_RX_BD_MISS) {
bad = 1;
dbg_print("> missed!\n");
}
if (rx_bdp[i].len_status & OETH_RX_BD_LATECOL) {
bad = 1;
dbg_print("> late collision!\n");
}
if (bad) {
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS;
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY;
}
else {
/*
* Process the incoming frame.
*/
unsigned char* buf = (unsigned char*)rx_bdp[i].addr;
dbg_print("> processing incoming packet\n");
pkt_len = rx_bdp[i].len_status >> 16;
dbg_print("> len_status: 0X%8X\n", rx_bdp[i].len_status);
dbg_print("> pkt_len_d: %d, pkt_len_h: 0X%08X\n", pkt_len, pkt_len);
user_recv(buf, pkt_len);
/* finish up */
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */
}
} else {
dbg_print("> empty!\n");
}
}
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
volatile oeth_bd *rx_bdp;
int pkt_len, i;
int bad = 0;
dbg_print("oeth_rx:\n");
rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
/* Find RX buffers marked as having received data */
for(i = 0; i < OETH_RXBD_NUM; i++)
{
dbg_print("> rxbd_num: %d\n", i);
bad=0;
/* Looking for buffer descriptors marked not empty */
if(!(rx_bdp[i].len_status & OETH_RX_BD_EMPTY)){
/* Check status for errors.
*/
dbg_print("> len_status: 0X%8X\n", rx_bdp[i].len_status);
if (rx_bdp[i].len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT)) {
bad = 1;
dbg_print("> short!\n");
}
if (rx_bdp[i].len_status & OETH_RX_BD_DRIBBLE) {
bad = 1;
dbg_print("> dribble!\n");
}
if (rx_bdp[i].len_status & OETH_RX_BD_CRCERR) {
bad = 1;
dbg_print("> CRC error!\n");
}
if (rx_bdp[i].len_status & OETH_RX_BD_OVERRUN) {
bad = 1;
dbg_print("> overrun!\n");
}
if (rx_bdp[i].len_status & OETH_RX_BD_MISS) {
bad = 1;
dbg_print("> missed!\n");
}
if (rx_bdp[i].len_status & OETH_RX_BD_LATECOL) {
bad = 1;
dbg_print("> late collision!\n");
}
if (bad) {
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS;
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY;
}
else {
/*
* Process the incoming frame.
*/
unsigned char* buf = (unsigned char*)rx_bdp[i].addr;
dbg_print("> processing incoming packet\n");
pkt_len = rx_bdp[i].len_status >> 16;
dbg_print("> len_status: 0X%8X\n", rx_bdp[i].len_status);
dbg_print("> pkt_len_d: %d, pkt_len_h: 0X%08X\n", pkt_len, pkt_len);
user_recv(buf, pkt_len);
/* finish up */
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */
}
} else {
dbg_print("> empty!\n");
}
}
}
static void oeth_tx(void)
{
volatile oeth_bd *tx_bd;
int i;
dbg_print("oeth_tx:\n");
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/
/* Go through the TX buffs, search for one that was just sent */
for(i = 0; i < OETH_TXBD_NUM; i++)
{
/* Looking for buffer NOT ready for transmit. and IRQ enabled */
if( (!(tx_bd[i].len_status & (OETH_TX_BD_READY))) && (tx_bd[i].len_status & (OETH_TX_BD_IRQ)) )
{
/* Single threaded so no chance we have detected a buffer that has had its IRQ bit set but not its BD_READ flag. Maybe this won't work in linux */
tx_bd[i].len_status &= ~OETH_TX_BD_IRQ;
/* Probably good to check for TX errors here */
}
}
return;
volatile oeth_bd *tx_bd;
int i;
dbg_print("oeth_tx:\n");
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/
/* Go through the TX buffs, search for one that was just sent */
for(i = 0; i < OETH_TXBD_NUM; i++)
{
/* Looking for buffer NOT ready for transmit. and IRQ enabled */
if( (!(tx_bd[i].len_status & (OETH_TX_BD_READY))) && (tx_bd[i].len_status & (OETH_TX_BD_IRQ)) )
{
/* Single threaded so no chance we have detected a buffer that has had its IRQ bit set but not its BD_READ flag. Maybe this won't work in linux */
tx_bd[i].len_status &= ~OETH_TX_BD_IRQ;
/* Probably good to check for TX errors here */
}
}
return;
}
/* The interrupt handler.
......@@ -106,52 +106,52 @@ static void oeth_tx(void)
void oeth_interrupt(void* arg)
{
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
dbg_print("oeth_interrupt:\n");
uint int_events;
int serviced;
serviced = 0;
/* Get the interrupt events that caused us to be here.
*/
int_events = regs->int_src;
regs->int_src = int_events;
dbg_print("> int_events = 0x%8X\n", int_events);
/* Handle receive event in its own function.
*/
if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) {
serviced |= 0x1;
dbg_print("> interrupt on rx line\n");
oeth_rx();
}
/* Handle transmit event in its own function.
*/
if (int_events & (OETH_INT_TXB | OETH_INT_TXE)) {
serviced |= 0x2;
dbg_print("> interrupt on tx line\n");
oeth_tx();
serviced |= 0x2;
}
/* Check for receive busy, i.e. packets coming but no place to
* put them.
*/
if (int_events & OETH_INT_BUSY) {
serviced |= 0x4;
dbg_print("> receive busy\n");
if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE))) {
oeth_rx();
}
}
dbg_print("> nothing\n");
return;
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
dbg_print("oeth_interrupt:\n");
uint int_events;
int serviced;
serviced = 0;
/* Get the interrupt events that caused us to be here.
*/
int_events = regs->int_src;
regs->int_src = int_events;
dbg_print("> int_events = 0x%8X\n", int_events);
/* Handle receive event in its own function.
*/
if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) {
serviced |= 0x1;
dbg_print("> interrupt on rx line\n");
oeth_rx();
}
/* Handle transmit event in its own function.
*/
if (int_events & (OETH_INT_TXB | OETH_INT_TXE)) {
serviced |= 0x2;
dbg_print("> interrupt on tx line\n");
oeth_tx();
serviced |= 0x2;
}
/* Check for receive busy, i.e. packets coming but no place to
* put them.
*/
if (int_events & OETH_INT_BUSY) {
serviced |= 0x4;
dbg_print("> receive busy\n");
if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE))) {
oeth_rx();
}
}
dbg_print("> nothing\n");
return;
}
embedded-sw/lib/ethmac/ethmac-rxtx.c
View file @ f2cb30f4
......@@ -97,7 +97,7 @@ struct oeth_private {
unsigned short tx_last; /* Next buffer to be checked if packet sent */
unsigned short tx_full; /* Buffer ring fuul indicator */
unsigned short rx_cur; /* Next buffer to be checked if packet
received */
received */
oeth_regs *regs; /* Address of controller registers. */
oeth_bd *rx_bd_base; /* Address of Rx BDs. */
......@@ -623,7 +623,7 @@ main ()
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */
/* clear tx_done, the tx interrupt handler will set it when it's been
transmitted */
transmitted */
tx_done = 0;
rx_done = 0;
......
embedded-sw/lib/ethmac/ethmac-rxtxcallresponse.c
View file @ f2cb30f4
......@@ -97,7 +97,7 @@ struct oeth_private {
unsigned short tx_last; /* Next buffer to be checked if packet sent */
unsigned short tx_full; /* Buffer ring fuul indicator */
unsigned short rx_cur; /* Next buffer to be checked if packet
received */
received */
oeth_regs *regs; /* Address of controller registers. */
oeth_bd *rx_bd_base; /* Address of Rx BDs. */
......@@ -627,7 +627,7 @@ main ()
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */
/* clear tx_done, the tx interrupt handler will set it when it's been
transmitted */
transmitted */
tx_done = 0;
rx_done = 0;
......
embedded-sw/lib/ethmac/ethmac.c
View file @ f2cb30f4
This diff is collapsed.
embedded-sw/lib/ethmac/ethmac.h
View file @ f2cb30f4
......@@ -45,37 +45,37 @@ typedef unsigned int uint;
/* Ethernet configuration registers */
typedef struct _oeth_regs {
uint moder; /* Mode Register */
uint int_src; /* Interrupt Source Register */
uint int_mask; /* Interrupt Mask Register */
uint ipgt; /* Back to Bak Inter Packet Gap Register */
uint ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */
uint ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */
uint packet_len; /* Packet Length Register (min. and max.) */
uint collconf; /* Collision and Retry Configuration Register */
uint tx_bd_num; /* Transmit Buffer Descriptor Number Register */
uint ctrlmoder; /* Control Module Mode Register */
uint miimoder; /* MII Mode Register */
uint miicommand; /* MII Command Register */
uint miiaddress; /* MII Address Register */
uint miitx_data; /* MII Transmit Data Register */
uint miirx_data; /* MII Receive Data Register */
uint miistatus; /* MII Status Register */
uint mac_addr0; /* MAC Individual Address Register 0 */
uint mac_addr1; /* MAC Individual Address Register 1 */
uint hash_addr0; /* Hash Register 0 */
uint hash_addr1; /* Hash Register 1 */
uint moder; /* Mode Register */
uint int_src; /* Interrupt Source Register */
uint int_mask; /* Interrupt Mask Register */
uint ipgt; /* Back to Bak Inter Packet Gap Register */
uint ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */
uint ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */
uint packet_len; /* Packet Length Register (min. and max.) */
uint collconf; /* Collision and Retry Configuration Register */
uint tx_bd_num; /* Transmit Buffer Descriptor Number Register */
uint ctrlmoder; /* Control Module Mode Register */
uint miimoder; /* MII Mode Register */
uint miicommand; /* MII Command Register */
uint miiaddress; /* MII Address Register */
uint miitx_data; /* MII Transmit Data Register */
uint miirx_data; /* MII Receive Data Register */
uint miistatus; /* MII Status Register */
uint mac_addr0; /* MAC Individual Address Register 0 */
uint mac_addr1; /* MAC Individual Address Register 1 */
uint hash_addr0; /* Hash Register 0 */
uint hash_addr1; /* Hash Register 1 */
} oeth_regs;
/* Ethernet buffer descriptor */
typedef struct _oeth_bd {
#if 0
ushort len; /* Buffer length */
ushort status; /* Buffer status */
ushort len; /* Buffer length */
ushort status; /* Buffer status */
#else
uint len_status;
uint len_status;
#endif
uint addr; /* Buffer address */
uint addr; /* Buffer address */
} oeth_bd;
// From board.h
......@@ -100,11 +100,11 @@ typedef struct _oeth_bd {
#define OETH_TX_BD_DEFER 0x0002 /* Tx BD Defer Status */
#define OETH_TX_BD_CARRIER 0x0001 /* Tx BD Carrier Sense Lost Status */
#define OETH_TX_BD_STATS (OETH_TX_BD_UNDERRUN | \
OETH_TX_BD_RETRY | \
OETH_TX_BD_RETLIM | \
OETH_TX_BD_LATECOL | \
OETH_TX_BD_DEFER | \
OETH_TX_BD_CARRIER)
OETH_TX_BD_RETRY | \
OETH_TX_BD_RETLIM | \
OETH_TX_BD_LATECOL | \
OETH_TX_BD_DEFER | \
OETH_TX_BD_CARRIER)
/* Rx BD */
#define OETH_RX_BD_EMPTY 0x8000 /* Rx BD Empty */
......@@ -120,13 +120,13 @@ typedef struct _oeth_bd {
#define OETH_RX_BD_CRCERR 0x0002 /* Rx BD CRC Error Status */
#define OETH_RX_BD_LATECOL 0x0001 /* Rx BD Late Collision Status */
#define OETH_RX_BD_STATS (OETH_RX_BD_MISS | \
OETH_RX_BD_OVERRUN | \
OETH_RX_BD_INVSIMB | \
OETH_RX_BD_DRIBBLE | \
OETH_RX_BD_TOOLONG | \
OETH_RX_BD_SHORT | \
OETH_RX_BD_CRCERR | \
OETH_RX_BD_LATECOL)
OETH_RX_BD_OVERRUN | \
OETH_RX_BD_INVSIMB | \
OETH_RX_BD_DRIBBLE | \
OETH_RX_BD_TOOLONG | \
OETH_RX_BD_SHORT | \
OETH_RX_BD_CRCERR | \
OETH_RX_BD_LATECOL)
/* MODER Register */
#define OETH_MODER_RXEN 0x00000001 /* Receive Enable */
......
embedded-sw/pp_printf/pp-printf.h
View file @ f2cb30f4
......@@ -5,17 +5,17 @@
#endif
extern int pp_printf(const char *fmt, ...)
__attribute__((format(printf,1,2)));
__attribute__((format(printf,1,2)));
extern int pp_sprintf(char *s, const char *fmt, ...)
__attribute__((format(printf,2,3)));
__attribute__((format(printf,2,3)));
extern int pp_vprintf(const char *fmt, va_list args);
extern int pp_vprintf(const char *fmt, va_list args);
extern int pp_vsprintf(char *buf, const char *, va_list)
__attribute__ ((format (printf, 2, 0)));
__attribute__ ((format (printf, 2, 0)));
/* This is what we rely on for output */
extern int puts(const char *s);
/* This is what we rely on for output */
extern int puts(const char *s);
embedded-sw/pp_printf/vsprintf-full.c
View file @ f2cb30f4
......@@ -225,9 +225,9 @@ static char *number(char *buf, unsigned long num, int base, int size, int precis
if (num == 0)
tmp[i++] = '0';
/* Generic code, for any base:
else do {
tmp[i++] = (digits[do_div(num,base)] | locase);
} while (num != 0);
else do {
tmp[i++] = (digits[do_div(num,base)] | locase);
} while (num != 0);
*/
else if (base != 10) { /* 8 or 16 */
int mask = base - 1;
......@@ -430,7 +430,7 @@ int pp_vsprintf(char *buf, const char *fmt, va_list args)
int field_width; /* width of output field */
int precision; /* min. # of digits for integers; max
number of chars for from string */
number of chars for from string */
int qualifier; /* 'h', 'l', or 'L' for integer fields */
/* 'z' support added 23/7/1999 S.H. */
/* 'z' changed to 'Z' --davidm 1/25/99 */
......
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