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Beam Positoning Monitor - Gateware
Commit ea2a6157 authored by Lucas Russo's avatar Lucas Russo
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modules/*/wb_trigger*/*: add sync with different clock domains 

Now, we can sync input/output pulses with different
clock domains.
parent 5b9f903d
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Showing with 185 additions and 58 deletions
hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd
View file @ ea2a6157
...@@ -1731,8 +1731,8 @@ package dbe_wishbone_pkg is ...@@ -1731,8 +1731,8 @@ package dbe_wishbone_pkg is
clk_i : in std_logic; clk_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
fs_clk_i : in std_logic; ref_clk_i : in std_logic;
fs_rst_n_i : in std_logic; ref_rst_n_i : in std_logic;
------------------------------- -------------------------------
---- Wishbone Control Interface signals ---- Wishbone Control Interface signals
...@@ -1778,8 +1778,9 @@ package dbe_wishbone_pkg is ...@@ -1778,8 +1778,9 @@ package dbe_wishbone_pkg is
( (
rst_n_i : in std_logic; rst_n_i : in std_logic;
clk_i : in std_logic; clk_i : in std_logic;
fs_clk_i : in std_logic;
fs_rst_n_i : in std_logic; ref_clk_i : in std_logic;
ref_rst_n_i : in std_logic;
----------------------------- -----------------------------
-- Wishbone signals -- Wishbone signals
...@@ -1815,14 +1816,19 @@ package dbe_wishbone_pkg is ...@@ -1815,14 +1816,19 @@ package dbe_wishbone_pkg is
-- Limit defined by wb_trigger_regs.vhd -- Limit defined by wb_trigger_regs.vhd
g_num_mux_interfaces : natural := 2; -- Number of wb_trigger_mux modules g_num_mux_interfaces : natural := 2; -- Number of wb_trigger_mux modules
g_out_resolver : string := "fanout"; -- Resolver policy for output triggers g_out_resolver : string := "fanout"; -- Resolver policy for output triggers
g_in_resolver : string := "or" -- Resolver policy for input triggers g_in_resolver : string := "or"; -- Resolver policy for input triggers
g_with_input_sync : boolean := true;
g_with_output_sync : boolean := true
); );
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
fs_clk_i : in std_logic; ref_clk_i : in std_logic;
fs_rst_n_i : in std_logic; ref_rst_n_i : in std_logic;
fs_clk_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
fs_rst_n_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
------------------------------- -------------------------------
---- Wishbone Control Interface signals ---- Wishbone Control Interface signals
...@@ -1882,14 +1888,20 @@ package dbe_wishbone_pkg is ...@@ -1882,14 +1888,20 @@ package dbe_wishbone_pkg is
-- Limit defined by wb_trigger_regs.vhd -- Limit defined by wb_trigger_regs.vhd
g_num_mux_interfaces : natural := 2; -- Number of wb_trigger_mux modules g_num_mux_interfaces : natural := 2; -- Number of wb_trigger_mux modules
g_out_resolver : string := "fanout"; -- Resolver policy for output triggers g_out_resolver : string := "fanout"; -- Resolver policy for output triggers
g_in_resolver : string := "or" -- Resolver policy for input triggers g_in_resolver : string := "or"; -- Resolver policy for input triggers
g_with_input_sync : boolean := true;
g_with_output_sync : boolean := true
); );
port port
( (
rst_n_i : in std_logic; clk_i : in std_logic;
clk_i : in std_logic; rst_n_i : in std_logic;
fs_clk_i : in std_logic;
fs_rst_n_i : in std_logic; ref_clk_i : in std_logic;
ref_rst_n_i : in std_logic;
fs_clk_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
fs_rst_n_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
----------------------------- -----------------------------
-- Wishbone signals -- Wishbone signals
......
hdl/modules/dbe_wishbone/wb_trigger/trigger_pkg.vhd
View file @ ea2a6157
...@@ -30,11 +30,18 @@ package trigger_pkg is ...@@ -30,11 +30,18 @@ package trigger_pkg is
g_trig_num : natural := 8; g_trig_num : natural := 8;
g_num_mux_interfaces : natural := 2; g_num_mux_interfaces : natural := 2;
g_out_resolver : string := "fanout"; g_out_resolver : string := "fanout";
g_in_resolver : string := "or" g_in_resolver : string := "or";
g_with_input_sync : boolean := true;
g_with_output_sync : boolean := true
); );
port ( port (
clk_i : in std_logic; -- Reference clock for physical component (e.g., backplane, board)
rst_n_i : in std_logic; ref_clk_i : in std_logic;
ref_rst_n_i : in std_logic;
-- Synchronization clocks for different domains
fs_clk_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
fs_rst_n_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
------------------------------- -------------------------------
--- Trigger ports --- Trigger ports
......
hdl/modules/dbe_wishbone/wb_trigger/trigger_resolver.vhd
View file @ ea2a6157
...@@ -40,6 +40,8 @@ use ieee.numeric_std.all; ...@@ -40,6 +40,8 @@ use ieee.numeric_std.all;
library work; library work;
-- Main Wishbone Definitions -- Main Wishbone Definitions
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
-- Common Cores
use work.gencores_pkg.all;
-- Custom Wishbone Modules -- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all; use work.dbe_wishbone_pkg.all;
-- Reset Synch -- Reset Synch
...@@ -52,19 +54,28 @@ entity trigger_resolver is ...@@ -52,19 +54,28 @@ entity trigger_resolver is
g_trig_num : natural := 8; g_trig_num : natural := 8;
g_num_mux_interfaces : natural := 2; g_num_mux_interfaces : natural := 2;
g_out_resolver : string := "fanout"; g_out_resolver : string := "fanout";
g_in_resolver : string := "or" g_in_resolver : string := "or";
g_with_input_sync : boolean := true;
g_with_output_sync : boolean := true
); );
port ( port (
clk_i : in std_logic; -- Reference clock for physical component (e.g., backplane, board)
rst_n_i : in std_logic; ref_clk_i : in std_logic;
ref_rst_n_i : in std_logic;
-- Synchronization clocks for different domains
fs_clk_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
fs_rst_n_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
------------------------------- -------------------------------
--- Trigger ports --- Trigger ports
------------------------------- -------------------------------
-- Synchronous with ref_clk
trig_resolved_out_o : out t_trig_channel_array(g_trig_num-1 downto 0); trig_resolved_out_o : out t_trig_channel_array(g_trig_num-1 downto 0);
trig_resolved_in_i : in t_trig_channel_array(g_trig_num-1 downto 0); trig_resolved_in_i : in t_trig_channel_array(g_trig_num-1 downto 0);
-- Synchronous with fs_clk_array_i(i)
trig_mux_out_o : out t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0); trig_mux_out_o : out t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0);
trig_mux_in_i : in t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0) trig_mux_in_i : in t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0)
); );
...@@ -73,6 +84,7 @@ end entity trigger_resolver; ...@@ -73,6 +84,7 @@ end entity trigger_resolver;
architecture rtl of trigger_resolver is architecture rtl of trigger_resolver is
signal trig_mux_out_int : t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0); signal trig_mux_out_int : t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0);
signal trig_mux_out_int_synched : t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0);
signal trig_mux_in_int : t_trig_channel_array(g_trig_num-1 downto 0); signal trig_mux_in_int : t_trig_channel_array(g_trig_num-1 downto 0);
-- Trigger ordered by interfaces -- Trigger ordered by interfaces
...@@ -80,6 +92,7 @@ architecture rtl of trigger_resolver is ...@@ -80,6 +92,7 @@ architecture rtl of trigger_resolver is
type t_trig_interface_pulses_array is array (natural range <>) of t_trig_interface_pulses; type t_trig_interface_pulses_array is array (natural range <>) of t_trig_interface_pulses;
signal trig_mux_in_interface_pulses : t_trig_interface_pulses_array(g_trig_num-1 downto 0); signal trig_mux_in_interface_pulses : t_trig_interface_pulses_array(g_trig_num-1 downto 0);
signal trig_mux_in_interface_pulses_synched : t_trig_interface_pulses_array(g_trig_num-1 downto 0);
-- From general-cores wb_crossbar module -- From general-cores wb_crossbar module
-- If any of the bits are '1', the whole thing is '1' -- If any of the bits are '1', the whole thing is '1'
...@@ -108,15 +121,19 @@ begin -- architecture rtl ...@@ -108,15 +121,19 @@ begin -- architecture rtl
report "[trigger_resolver] only g_in_resolver equal to ""or"" is supported!" report "[trigger_resolver] only g_in_resolver equal to ""or"" is supported!"
severity failure; severity failure;
-----------------------------------------------------------------------------
-- Resolved triggers to Muxed triggers
-----------------------------------------------------------------------------
-- Generate Output -- Generate Output
gen_output_interfaces : for i in 0 to g_num_mux_interfaces-1 generate gen_output_interfaces : for i in 0 to g_num_mux_interfaces-1 generate
gen_output_trigger_channels : for j in 0 to g_trig_num-1 generate gen_output_trigger_channels : for j in 0 to g_trig_num-1 generate
gen_output_resolver_fanout : if g_out_resolver = "fanout" generate gen_output_resolver_fanout : if g_out_resolver = "fanout" generate
p_output : process (clk_i) p_output : process (ref_clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(ref_clk_i) then
if rst_n_i = '0' then if ref_rst_n_i = '0' then
trig_mux_out_int (i, j) <= c_trig_channel_dummy; trig_mux_out_int (i, j) <= c_trig_channel_dummy;
else else
trig_mux_out_int (i, j) <= trig_resolved_in_i(j); trig_mux_out_int (i, j) <= trig_resolved_in_i(j);
...@@ -128,7 +145,43 @@ begin -- architecture rtl ...@@ -128,7 +145,43 @@ begin -- architecture rtl
end generate; end generate;
end generate; end generate;
trig_mux_out_o <= trig_mux_out_int; -- Resynchronize pulses to ref_clk domain
gen_sync_output_interfaces : for i in 0 to g_num_mux_interfaces-1 generate
gen_sync_output_trigger_channels : for j in 0 to g_trig_num-1 generate
gen_with_output_sync : if g_with_output_sync generate
cmp_gc_pulse_synchronizer2 : gc_pulse_synchronizer2
port map (
-- pulse input clock
clk_in_i => ref_clk_i,
rst_in_n_i => ref_rst_n_i,
-- pulse output clock
clk_out_i => fs_clk_array_i(i),
rst_out_n_i => fs_rst_n_array_i(i),
-- pulse input ready (clk_in_i domain). When HI, a pulse coming to d_p_i will be
-- correctly transferred to q_p_o.
d_ready_o => open,
-- pulse input (clk_in_i domain)
d_p_i => trig_mux_out_int(i, j).pulse,
-- pulse output (clk_out_i domain)
q_p_o => trig_mux_out_int_synched(i, j).pulse
);
end generate;
gen_without_output_sync : if not (g_with_output_sync) generate
trig_mux_out_int_synched(i, j) <= trig_mux_out_int(i, j);
end generate;
end generate;
end generate;
trig_mux_out_o <= trig_mux_out_int_synched;
-----------------------------------------------------------------------------
-- Muxed triggers to Resolved triggers
-----------------------------------------------------------------------------
-- Reorder input channels -- Reorder input channels
gen_reorder_trigger_channels : for j in 0 to g_trig_num-1 generate gen_reorder_trigger_channels : for j in 0 to g_trig_num-1 generate
...@@ -139,16 +192,47 @@ begin -- architecture rtl ...@@ -139,16 +192,47 @@ begin -- architecture rtl
end generate; end generate;
end generate; end generate;
-- Generate Inputs -- Resynchronize pulses to ref_clk domain
gen_sync_input_trigger_channels : for j in 0 to g_trig_num-1 generate
gen_sync_input_interfaces : for i in 0 to g_num_mux_interfaces-1 generate
gen_with_input_sync : if g_with_input_sync generate
cmp_gc_pulse_synchronizer2 : gc_pulse_synchronizer2
port map (
-- pulse input clock
clk_in_i => fs_clk_array_i(i),
rst_in_n_i => fs_rst_n_array_i(i),
-- pulse output clock
clk_out_i => ref_clk_i,
rst_out_n_i => ref_rst_n_i,
-- pulse input ready (clk_in_i domain). When HI, a pulse coming to d_p_i will be
-- correctly transferred to q_p_o.
d_ready_o => open,
-- pulse input (clk_in_i domain)
d_p_i => trig_mux_in_interface_pulses(j)(i),
-- pulse output (clk_out_i domain)
q_p_o => trig_mux_in_interface_pulses_synched(j)(i)
);
end generate;
gen_without_input_sync : if not (g_with_input_sync) generate
trig_mux_in_interface_pulses_synched(j)(i) <= trig_mux_in_interface_pulses(j)(i);
end generate;
end generate;
end generate;
-- Generate Inputs (synchronous to fs_clk_array_i(j))
gen_input_trigger_channels : for j in 0 to g_trig_num-1 generate gen_input_trigger_channels : for j in 0 to g_trig_num-1 generate
gen_input_resolver_or : if g_in_resolver = "or" generate gen_input_resolver_or : if g_in_resolver = "or" generate
p_input : process (clk_i) p_input : process (ref_clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(ref_clk_i) then
if rst_n_i = '0' then if ref_rst_n_i = '0' then
trig_mux_in_int(j) <= c_trig_channel_dummy; trig_mux_in_int(j) <= c_trig_channel_dummy;
else else
trig_mux_in_int(j).pulse <= f_vector_OR(trig_mux_in_interface_pulses(j)); trig_mux_in_int(j).pulse <= f_vector_OR(trig_mux_in_interface_pulses_synched(j));
end if; end if;
end if; end if;
end process; end process;
......
hdl/modules/dbe_wishbone/wb_trigger/wb_trigger.vhd
View file @ ea2a6157
...@@ -62,14 +62,19 @@ entity wb_trigger is ...@@ -62,14 +62,19 @@ entity wb_trigger is
-- Limit defined by wb_trigger_regs.vhd -- Limit defined by wb_trigger_regs.vhd
g_num_mux_interfaces : natural := 2; -- Number of wb_trigger_mux modules g_num_mux_interfaces : natural := 2; -- Number of wb_trigger_mux modules
g_out_resolver : string := "fanout"; -- Resolver policy for output triggers g_out_resolver : string := "fanout"; -- Resolver policy for output triggers
g_in_resolver : string := "or" -- Resolver policy for input triggers g_in_resolver : string := "or"; -- Resolver policy for input triggers
g_with_input_sync : boolean := true;
g_with_output_sync : boolean := true
); );
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
fs_clk_i : in std_logic; ref_clk_i : in std_logic;
fs_rst_n_i : in std_logic; ref_rst_n_i : in std_logic;
fs_clk_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
fs_rst_n_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
------------------------------- -------------------------------
---- Wishbone Control Interface signals ---- Wishbone Control Interface signals
...@@ -144,8 +149,9 @@ begin -- architecture rtl ...@@ -144,8 +149,9 @@ begin -- architecture rtl
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
fs_clk_i => fs_clk_i,
fs_rst_n_i => fs_rst_n_i, ref_clk_i => ref_clk_i,
ref_rst_n_i => ref_rst_n_i,
wb_adr_i => wb_trigger_iface_adr_i, wb_adr_i => wb_trigger_iface_adr_i,
wb_dat_i => wb_trigger_iface_dat_i, wb_dat_i => wb_trigger_iface_dat_i,
...@@ -170,11 +176,16 @@ begin -- architecture rtl ...@@ -170,11 +176,16 @@ begin -- architecture rtl
g_trig_num => g_trig_num, g_trig_num => g_trig_num,
g_num_mux_interfaces => g_num_mux_interfaces, g_num_mux_interfaces => g_num_mux_interfaces,
g_out_resolver => g_out_resolver, g_out_resolver => g_out_resolver,
g_in_resolver => g_in_resolver g_in_resolver => g_in_resolver,
g_with_input_sync => g_with_input_sync,
g_with_output_sync => g_with_output_sync
) )
port map ( port map (
clk_i => fs_clk_i, ref_clk_i => ref_clk_i,
rst_n_i => fs_rst_n_i, ref_rst_n_i => ref_rst_n_i,
fs_clk_array_i => fs_clk_array_i,
fs_rst_n_array_i => fs_rst_n_array_i,
trig_resolved_out_o => trig_in_resolved, trig_resolved_out_o => trig_in_resolved,
trig_resolved_in_i => trig_out_resolved, trig_resolved_in_i => trig_out_resolved,
...@@ -204,8 +215,9 @@ begin -- architecture rtl ...@@ -204,8 +215,9 @@ begin -- architecture rtl
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
fs_clk_i => fs_clk_i,
fs_rst_n_i => fs_rst_n_i, fs_clk_i => fs_clk_array_i(i),
fs_rst_n_i => fs_rst_n_array_i(i),
wb_adr_i => wb_trigger_mux_adr_i((i+1)*c_wishbone_address_width-1 downto i*c_wishbone_address_width), wb_adr_i => wb_trigger_mux_adr_i((i+1)*c_wishbone_address_width-1 downto i*c_wishbone_address_width),
wb_dat_i => wb_trigger_mux_dat_i((i+1)*c_wishbone_data_width-1 downto i*c_wishbone_data_width), wb_dat_i => wb_trigger_mux_dat_i((i+1)*c_wishbone_data_width-1 downto i*c_wishbone_data_width),
......
hdl/modules/dbe_wishbone/wb_trigger/xwb_trigger.vhd
View file @ ea2a6157
...@@ -22,14 +22,20 @@ entity xwb_trigger is ...@@ -22,14 +22,20 @@ entity xwb_trigger is
-- Limit defined by wb_trigger_regs.vhd -- Limit defined by wb_trigger_regs.vhd
g_num_mux_interfaces : natural := 2; -- Number of wb_trigger_mux modules g_num_mux_interfaces : natural := 2; -- Number of wb_trigger_mux modules
g_out_resolver : string := "fanout"; -- Resolver policy for output triggers g_out_resolver : string := "fanout"; -- Resolver policy for output triggers
g_in_resolver : string := "or" -- Resolver policy for input triggers g_in_resolver : string := "or"; -- Resolver policy for input triggers
g_with_input_sync : boolean := true;
g_with_output_sync : boolean := true
); );
port port
( (
rst_n_i : in std_logic; clk_i : in std_logic;
clk_i : in std_logic; rst_n_i : in std_logic;
fs_clk_i : in std_logic;
fs_rst_n_i : in std_logic; ref_clk_i : in std_logic;
ref_rst_n_i : in std_logic;
fs_clk_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
fs_rst_n_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
----------------------------- -----------------------------
-- Wishbone signals -- Wishbone signals
...@@ -93,14 +99,19 @@ begin ...@@ -93,14 +99,19 @@ begin
g_rcv_intern_num => g_rcv_intern_num, g_rcv_intern_num => g_rcv_intern_num,
g_num_mux_interfaces => g_num_mux_interfaces, g_num_mux_interfaces => g_num_mux_interfaces,
g_out_resolver => g_out_resolver, g_out_resolver => g_out_resolver,
g_in_resolver => g_in_resolver g_in_resolver => g_in_resolver,
g_with_input_sync => g_with_input_sync,
g_with_output_sync => g_with_output_sync
) )
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
ref_clk_i => ref_clk_i,
ref_rst_n_i => ref_rst_n_i,
fs_clk_i => fs_clk_i, fs_clk_array_i => fs_clk_array_i,
fs_rst_n_i => fs_rst_n_i, fs_rst_n_array_i => fs_rst_n_array_i,
wb_trigger_iface_adr_i => wb_slv_trigger_iface_i.adr, wb_trigger_iface_adr_i => wb_slv_trigger_iface_i.adr,
wb_trigger_iface_dat_i => wb_slv_trigger_iface_i.dat, wb_trigger_iface_dat_i => wb_slv_trigger_iface_i.dat,
......
hdl/modules/dbe_wishbone/wb_trigger_iface/wb_trigger_iface.vhd
View file @ ea2a6157
...@@ -69,8 +69,8 @@ entity wb_trigger_iface is ...@@ -69,8 +69,8 @@ entity wb_trigger_iface is
clk_i : in std_logic; clk_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
fs_clk_i : in std_logic; ref_clk_i : in std_logic;
fs_rst_n_i : in std_logic; ref_rst_n_i : in std_logic;
------------------------------- -------------------------------
---- Wishbone Control Interface signals ---- Wishbone Control Interface signals
...@@ -234,7 +234,7 @@ begin -- architecture rtl ...@@ -234,7 +234,7 @@ begin -- architecture rtl
port map ( port map (
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
clk_sys_i => clk_i, clk_sys_i => clk_i,
fs_clk_i => fs_clk_i, fs_clk_i => ref_clk_i,
wb_clk_i => clk_i, wb_clk_i => clk_i,
wb_adr_i => wb_slv_adp_out.adr(6 downto 0), wb_adr_i => wb_slv_adp_out.adr(6 downto 0),
wb_dat_i => wb_slv_adp_out.dat, wb_dat_i => wb_slv_adp_out.dat,
...@@ -492,8 +492,8 @@ begin -- architecture rtl ...@@ -492,8 +492,8 @@ begin -- architecture rtl
generic map ( generic map (
g_width_bus_size => c_transm_pulse_len) g_width_bus_size => c_transm_pulse_len)
port map ( port map (
clk_i => fs_clk_i, clk_i => ref_clk_i,
rst_n_i => fs_rst_n_i, rst_n_i => ref_rst_n_i,
pulse_i => transm_pulse_bus(i).pulse, pulse_i => transm_pulse_bus(i).pulse,
pulse_width_i => unsigned(ch_regs_out(i).ch_cfg_transm_len), pulse_width_i => unsigned(ch_regs_out(i).ch_cfg_transm_len),
extended_o => extended_transm(i)); extended_o => extended_transm(i));
...@@ -503,8 +503,8 @@ begin -- architecture rtl ...@@ -503,8 +503,8 @@ begin -- architecture rtl
g_glitch_len_width => c_rcv_pulse_len, g_glitch_len_width => c_rcv_pulse_len,
g_sync_edge => g_sync_edge) g_sync_edge => g_sync_edge)
port map ( port map (
clk_i => fs_clk_i, clk_i => ref_clk_i,
rst_n_i => fs_rst_n_i, rst_n_i => ref_rst_n_i,
len_i => ch_regs_out(i).ch_cfg_rcv_len, len_i => ch_regs_out(i).ch_cfg_rcv_len,
data_i => extended_rcv(i), data_i => extended_rcv(i),
pulse_o => rcv_pulse_bus(i).pulse); pulse_o => rcv_pulse_bus(i).pulse);
...@@ -529,7 +529,7 @@ begin -- architecture rtl ...@@ -529,7 +529,7 @@ begin -- architecture rtl
generic map ( generic map (
g_output_width => c_counter_width) g_output_width => c_counter_width)
port map ( port map (
clk_i => fs_clk_i, clk_i => ref_clk_i,
rst_n_i => ch_regs_out(i).ch_ctl_rcv_count_rst_n, rst_n_i => ch_regs_out(i).ch_ctl_rcv_count_rst_n,
ce_i => '1', ce_i => '1',
up_i => rcv_pulse_bus(i).pulse, up_i => rcv_pulse_bus(i).pulse,
...@@ -540,7 +540,7 @@ begin -- architecture rtl ...@@ -540,7 +540,7 @@ begin -- architecture rtl
generic map ( generic map (
g_output_width => c_counter_width) g_output_width => c_counter_width)
port map ( port map (
clk_i => fs_clk_i, clk_i => ref_clk_i,
rst_n_i => ch_regs_out(i).ch_ctl_transm_count_rst_n, rst_n_i => ch_regs_out(i).ch_ctl_transm_count_rst_n,
ce_i => '1', ce_i => '1',
up_i => transm_pulse_bus(i).pulse, up_i => transm_pulse_bus(i).pulse,
......
hdl/modules/dbe_wishbone/wb_trigger_iface/xwb_trigger_iface.vhd
View file @ ea2a6157
...@@ -22,8 +22,9 @@ entity xwb_trigger_iface is ...@@ -22,8 +22,9 @@ entity xwb_trigger_iface is
( (
rst_n_i : in std_logic; rst_n_i : in std_logic;
clk_i : in std_logic; clk_i : in std_logic;
fs_clk_i : in std_logic;
fs_rst_n_i : in std_logic; ref_clk_i : in std_logic;
ref_rst_n_i : in std_logic;
----------------------------- -----------------------------
-- Wishbone signals -- Wishbone signals
......
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