Commit ccc7d66e authored by Lucas Russo's avatar Lucas Russo

emb-sw/*: small fixes, probably due to a faulty merge

parent 00c8d8bd
......@@ -12,7 +12,7 @@
// Global SPI handler.
spi_t **spi;
uint32_t *spi_config;
static uint32_t *spi_config;
int spi_init(void)
{
......@@ -67,7 +67,7 @@ void spi_exit(void)
int oc_spi_poll(unsigned int id)
{
return spi[id]->CTRL & SPI_CTRL_BSY;
return (spi[id]->CTRL & SPI_CTRL_BSY) ? 1 : 0;
}
int oc_spi_three_mode(unsigned int id)
......
......@@ -63,16 +63,6 @@ static void fmc516_isla216_writew_raw(uint32_t val, int ss)
void fmc516_isla216_write_instaddr(int addr, int length, int read, int ss)
{
oc_spi_txrx(FMC516_LMK02000_SPI_ID, FMC516_LMK02000_CS,
FMC516_LMK02000_SIZE, val, NULL);
}
// No readback is available for lmk02000
/*
int fmc516_lmk02000_read_reg(int addr)
{
}
*/
uint32_t fmc516_isla216_reg;
// 1-byte length
......@@ -146,7 +136,7 @@ void fmc516_isla216_write_n(int val, int addr, int length, int ss)
static void fmc516_isla216_load_regset(const struct default_dev_regs_t *regs, int ss)
{
int i = 0;
int i = 0;
while (regs[i].type != REGS_DEFAULT_END){
if (regs[i].type == REGS_DEFAULT_INIT)
......
......@@ -10,31 +10,13 @@
// isla216p25 has 8-bit value and 13-bit register address
const struct default_dev_regs_t isla216p25_regs_default[] =
{
{REGS_DEFAULT_INIT, 4, 0x0, 1 << 31 },
{REGS_DEFAULT_INIT, 4, 0x0, 1 << 8 },
{REGS_DEFAULT_NO_INIT, 4, 0x1, 0 },
{REGS_DEFAULT_INIT, 4, 0x2, (1<<16)|(1<<8)|2 },
{REGS_DEFAULT_NO_INIT, 4, 0x3, 0 },
{REGS_DEFAULT_INIT, 4, 0x4, (1<<16)|(1<<8)| 4 },
{REGS_DEFAULT_INIT, 4, 0x5, (1<<16)|(1<<8)| 5 },
{REGS_DEFAULT_INIT, 4, 0x6, (1<<16)|(1<<8)| 6 },
{REGS_DEFAULT_INIT, 4, 0x7, (1<<16)|(1<<8)| 7 },
/*
{REGS_TYPE_RESERVED, 4, 0x8, 0 },
{REGS_TYPE_RESERVED, 4, 0x9, 0 },
{REGS_TYPE_RESERVED, 4, 0xa, 0 },
*/
{REGS_DEFAULT_NO_INIT, 4, 0xb, 0 },
/*
{REGS_TYPE_RESERVED, 4, 0xc, 0 },
{REGS_TYPE_RESERVED, 4, 0xd, 0 },
*/
{REGS_DEFAULT_INIT, 4, 0xe, 0x2b100100|14 },
{REGS_DEFAULT_NO_INIT, 4, 0xf, 0x4003e800|15 },
{REGS_DEFAULT_END, 0, 0 , 0 }
/*
{REGS_DEFAULT_INIT, 1, 0x0, 1 << 1 },
{REGS_DEFAULT_INIT, 1, 0x0, 1 << 0 },
*/
{REGS_DEFAULT_INIT, 1, 0x00, 1 << 5 },
{REGS_DEFAULT_INIT, 1, 0x00, 0 << 5 },
{REGS_DEFAULT_INIT, 1, 0x2b, 1 << 0 },
{REGS_DEFAULT_INIT, 1, 0x72, 1 << 0 },
{REGS_DEFAULT_END, 0, 0 , 0 }
};
......@@ -24,6 +24,9 @@
#define SPI_REG_DIVIDER 0x00000014
#define SPI_REG_SS 0x00000018
#define SPI_CTRL_THREE_WIRE (1<<16)
#define SPI_CTRL_RES2 (1<<15)
#define SPI_CTRL_DIR (1<<14)
#define SPI_CTRL_ASS (1<<13)
#define SPI_CTRL_IE (1<<12)
#define SPI_CTRL_LSB (1<<11)
......
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