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Commit c1ba5825 authored by Lucas Russo's avatar Lucas Russo
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testbench/*/wb_acq_core/*: update Manifest to work with new hdlmake 3

parent b20eb1aa
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Showing with 6 additions and 7 deletions
hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/Manifest.py
View file @ c1ba5825
......@@ -3,6 +3,7 @@ target = "xilinx"
syn_device = "xc7a200t"
sim_tool = "modelsim"
top_module = "wb_acq_core_tb"
sim_top = "wb_acq_core_tb"
modules = {"local" : [
"../../../../../../modules/dbe_wishbone",
......@@ -10,19 +11,17 @@ modules = {"local" : [
"../../../../../../modules/rffe_top",
"../../../../../../modules/fabric",
"../../../../../../modules/fmc_adc_common",
# "../../../../../../modules/pcie",
"../../../../../../ip_cores/general-cores",
"../../../../../../ip_cores/etherbone-core",
"../../../../../../platform",
"../../../../../../sim",
"../../../../../../sim/ddr_model",
"../../../../../../platform/artix7/afc_v3"]}
files = ["wb_acq_core_tb.v", "axi_interconnect_wrapper.vhd", "ddr_core_wrapper.vhd", "defines.v", "timescale.v",
files = ["wb_acq_core_tb.v", "axi_interconnect_wrapper.vhd", "ddr_core_wrapper.vhd",
"clk_rst.v", "../../../../../../sim/wishbone_test_master.v",
"../../../../../../../../../../../opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/glbl.v"]
"/opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/glbl.v"]
include_dirs = ["../../../../../../sim", "../../../../../../sim/regs", "../../../../../../sim/ddr_model",
"../../../../../../platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog"]
include_dirs = ["../../../../../../sim", "../../../../../../sim/regs", "../../../../../../sim/ddr_model/artix7",
"../../../../../../platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog", "."]
vlog_opt = "+incdir+../../../../../../sim/regs +incdir+../../../../../../sim +incdir+../../../../../../sim/ddr_model +incdir+../../../../../../platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog"
vlog_opt = "+incdir+../../../../../../sim/regs +incdir+../../../../../../sim +incdir+../../../../../../sim/ddr_model/artix7 +incdir+../../../../../../platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog +incdir+."
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