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Beam Positoning Monitor - Gateware
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Beam Positoning Monitor - Gateware
Commits
c00c28df
Commit
c00c28df
authored
Jun 04, 2018
by
Lucas Russo
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Merge branch 'devel'
parents
91ebf0c8
99e041be
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8 changed files
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178 additions
and
42 deletions
+178
-42
dsp-cores
hdl/ip_cores/dsp-cores
+1
-1
.gitignore
hdl/syn/.gitignore
+22
-0
Manifest.py
hdl/syn/afc_v3/vivado/dbe_bpm2_bo_sirius/Manifest.py
+2
-0
Manifest.py
hdl/syn/afc_v3/vivado/dbe_bpm2_sr_sirius/Manifest.py
+2
-0
Manifest.py
hdl/syn/afc_v3/vivado/dbe_bpm2_sr_uvx/Manifest.py
+2
-0
Manifest.py
hdl/syn/afc_v3/vivado/dbe_bpm_sr_uvx/Manifest.py
+2
-0
Manifest.py
hdl/syn/afc_v3/vivado/dbe_pbpm/Manifest.py
+2
-0
dbe_bpm_gen.vhd
hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd
+145
-41
No files found.
dsp-cores
@
934084fd
Subproject commit
55d25754c16e91682500948679bd330de27f595c
Subproject commit
934084fdda0e2a152833fd7478fba05fa941d8d8
hdl/syn/.gitignore
View file @
c00c28df
...
...
@@ -68,3 +68,25 @@ planAhead_run_*/
*.srcs/
*.jou
*.log
# hdlmake stuff
*tcl_bitstream
*tcl_map
*tcl_par
*tcl_synthesize
*tcl_translate
*bitstream
*map
*par
*synthesize
*translate
*bitstream.tcl
*map.tcl
*par.tcl
*synthesize.tcl
*translate.tcl
*project.tcl
*files.tcl
hdl/syn/afc_v3/vivado/dbe_bpm2_bo_sirius/Manifest.py
View file @
c00c28df
target
=
"xilinx"
action
=
"synthesis"
language
=
"vhdl"
syn_device
=
"xc7a200t"
syn_grade
=
"-2"
syn_package
=
"ffg1156"
...
...
hdl/syn/afc_v3/vivado/dbe_bpm2_sr_sirius/Manifest.py
View file @
c00c28df
target
=
"xilinx"
action
=
"synthesis"
language
=
"vhdl"
syn_device
=
"xc7a200t"
syn_grade
=
"-2"
syn_package
=
"ffg1156"
...
...
hdl/syn/afc_v3/vivado/dbe_bpm2_sr_uvx/Manifest.py
View file @
c00c28df
target
=
"xilinx"
action
=
"synthesis"
language
=
"vhdl"
syn_device
=
"xc7a200t"
syn_grade
=
"-2"
syn_package
=
"ffg1156"
...
...
hdl/syn/afc_v3/vivado/dbe_bpm_sr_uvx/Manifest.py
View file @
c00c28df
target
=
"xilinx"
action
=
"synthesis"
language
=
"vhdl"
syn_device
=
"xc7a200t"
syn_grade
=
"-2"
syn_package
=
"ffg1156"
...
...
hdl/syn/afc_v3/vivado/dbe_pbpm/Manifest.py
View file @
c00c28df
target
=
"xilinx"
action
=
"synthesis"
language
=
"vhdl"
syn_device
=
"xc7a200t"
syn_grade
=
"-2"
syn_package
=
"ffg1156"
...
...
hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd
View file @
c00c28df
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