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Beam Positoning Monitor - Gateware
Commit b9863df0 authored by Lucas Russo's avatar Lucas Russo
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emb-sw/*: update fmc516 register fields

parent a0afecef
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embedded-sw/dbe.vhd
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embedded-sw/fmc/fmc516/fmc516.c
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......@@ -94,24 +94,24 @@ void fmc516_sweep_delays(unsigned int id)
int commit = 1;
int i, j;
dbg_print("> ADC%d data delay: %d...\n", 0, FMC516_CH0_CTL_DATA_CHAIN_DLY_R(fmc516[id]->CH0_CTL));
dbg_print("> ADC%d data delay: %d...\n", 1, FMC516_CH1_CTL_DATA_CHAIN_DLY_R(fmc516[id]->CH1_CTL));
dbg_print("> ADC%d data delay: %d...\n", 2, FMC516_CH2_CTL_DATA_CHAIN_DLY_R(fmc516[id]->CH2_CTL));
dbg_print("> ADC%d data delay: %d...\n", 3, FMC516_CH3_CTL_DATA_CHAIN_DLY_R(fmc516[id]->CH3_CTL));
dbg_print("> ADC%d data delay: %d...\n", 0, FMC516_CH0_FN_DLY_DATA_CHAIN_DLY_R(fmc516[id]->CH0_FN_DLY));
dbg_print("> ADC%d data delay: %d...\n", 1, FMC516_CH1_FN_DLY_DATA_CHAIN_DLY_R(fmc516[id]->CH1_FN_DLY));
dbg_print("> ADC%d data delay: %d...\n", 2, FMC516_CH2_FN_DLY_DATA_CHAIN_DLY_R(fmc516[id]->CH2_FN_DLY));
dbg_print("> ADC%d data delay: %d...\n", 3, FMC516_CH3_FN_DLY_DATA_CHAIN_DLY_R(fmc516[id]->CH3_FN_DLY));
//for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
//for (j = 0; j < 32; ++j) {
// dbg_print("> sweeping ADC%d clk delay values: %d...\n", 1, j);
// fmc516_adj_delay(id, FMC516_ISLA216_ADC1, -1, j, commit);
// delay(80000000);
// dbg_print("> ADC%d data delay: %d...\n", 0, FMC516_CH0_CTL_CLK_CHAIN_DLY_R(fmc516[id]->CH0_CTL));
// dbg_print("> ADC%d data delay: %d...\n", 0, FMC516_CH0_CTL_CLK_CHAIN_DLY_R(fmc516[id]->CH0_FN_DLY));
//}
//for (j = 0; j < 32; ++j) {
// dbg_print("> sweeping ADC%d clk delay values: %d...\n", 2, j);
// fmc516_adj_delay(id, FMC516_ISLA216_ADC2, -1, j, commit);
// delay(150000000);
// dbg_print("> ADC%d data delay: %d...\n", 2, FMC516_CH2_CTL_CLK_CHAIN_DLY_R(fmc516[id]->CH2_CTL));
// dbg_print("> ADC%d data delay: %d...\n", 2, FMC516_CH2_CTL_CLK_CHAIN_DLY_R(fmc516[id]->CH2_FN_DLY));
//}
//}
}
......@@ -134,20 +134,20 @@ void fmc516_adj_delay(unsigned int id, int ch, int clk_dly, int data_dly, int co
// Find the correct ADC instance to operate on
switch(ch) {
case FMC516_ISLA216_ADC0:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_FN_DLY;
break;
case FMC516_ISLA216_ADC1:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH1_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH1_FN_DLY;
break;
case FMC516_ISLA216_ADC2:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH2_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH2_FN_DLY;
break;
case FMC516_ISLA216_ADC3:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH3_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH3_FN_DLY;
break;
default:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_FN_DLY;
}
// Read the register value once
......@@ -157,15 +157,15 @@ void fmc516_adj_delay(unsigned int id, int ch, int clk_dly, int data_dly, int co
/* All Read/Write macros are the same for all channels. Use the first one */
if (clk_dly != -1) {
/* Clear clk delay bits and write the desired value*/
adc_ctl_reg = (adc_ctl_reg & ~FMC516_CH0_CTL_CLK_CHAIN_DLY_MASK) |
FMC516_CH0_CTL_CLK_CHAIN_DLY_W(clk_dly);
adc_ctl_reg = (adc_ctl_reg & ~FMC516_CH0_FN_DLY_CLK_CHAIN_DLY_MASK) |
FMC516_CH0_FN_DLY_CLK_CHAIN_DLY_W(clk_dly);
}
if (data_dly != -1) {
/* Clear clk delay bits and write the desired value*/
adc_ctl_reg = (adc_ctl_reg & ~FMC516_CH0_CTL_DATA_CHAIN_DLY_MASK) |
FMC516_CH0_CTL_DATA_CHAIN_DLY_W(data_dly);
adc_ctl_reg = (adc_ctl_reg & ~FMC516_CH0_FN_DLY_DATA_CHAIN_DLY_MASK) |
FMC516_CH0_FN_DLY_DATA_CHAIN_DLY_W(data_dly);
}
......@@ -240,38 +240,44 @@ void fmc516_fe_rg_dly(unsigned int id, int ch, int fe_dly_d1, int fe_dly_d2,
switch(ch) {
case FMC516_ISLA216_ADC0:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_DLY_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_CS_DLY;
break;
case FMC516_ISLA216_ADC1:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH1_DLY_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH1_CS_DLY;
break;
case FMC516_ISLA216_ADC2:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH2_DLY_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH2_CS_DLY;
break;
case FMC516_ISLA216_ADC3:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH3_DLY_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH3_CS_DLY;
break;
default:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_DLY_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_CS_DLY;
}
// Read register value once
dly_ctl_reg = *fmc_ch_handler;
if (fe_dly_d2)
dly_ctl_reg |= (dly_ctl_reg & ~FMC516_CH0_DLY_CTL_FE_DLY_MASK) |
FMC516_CH0_DLY_CTL_FE_DLY_W(0x3);
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_FE_DLY_MASK) |
FMC516_CH0_CS_DLY_FE_DLY_W(0x3);
else if (fe_dly_d1)
dly_ctl_reg |= (dly_ctl_reg & ~FMC516_CH0_DLY_CTL_FE_DLY_MASK) |
FMC516_CH0_DLY_CTL_FE_DLY_W(0x1);
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_FE_DLY_MASK) |
FMC516_CH0_CS_DLY_FE_DLY_W(0x1);
else
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_FE_DLY_MASK) |
FMC516_CH0_CS_DLY_FE_DLY_W(0x0);
if (rg_dly_d2)
dly_ctl_reg |= (dly_ctl_reg & ~FMC516_CH0_DLY_CTL_RG_DLY_MASK) |
FMC516_CH0_DLY_CTL_RG_DLY_W(0x3);
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_RG_DLY_MASK) |
FMC516_CH0_CS_DLY_RG_DLY_W(0x3);
else if (rg_dly_d1)
dly_ctl_reg |= (dly_ctl_reg & ~FMC516_CH0_DLY_CTL_RG_DLY_MASK) |
FMC516_CH0_DLY_CTL_RG_DLY_W(0x1);
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_RG_DLY_MASK) |
FMC516_CH0_CS_DLY_RG_DLY_W(0x1);
else
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_RG_DLY_MASK) |
FMC516_CH0_CS_DLY_RG_DLY_W(0x0);
// Write register value once
*fmc_ch_handler = dly_ctl_reg;
......
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