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Beam Positoning Monitor - Gateware
Commit b139cd5a authored by Lucas Russo's avatar Lucas Russo
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all: fix identation at the beggining of the line 

This identation fix was done with the following command:

find . -type f -regextype posix-extended -iregex ".*(\.c|\.h|\.vhd)" | \
	xargs sed -i 's/  /\t/g'
parent 2071e175
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Showing with 8111 additions and 8129 deletions
embedded-sw/boards/ml605/board.c
View file @ b139cd5a
......@@ -4,18 +4,18 @@
int board_init()
{
return 0;
return 0;
}
int board_update()
{
return 0;
return 0;
}
/* Each loop iteration takes 4 cycles.
* It runs at 100MHz (LM32 clock).
/* Each loop iteration takes 4 cycles.
* It runs at 100MHz (LM32 clock).
*/
int delay(int x)
{
while(x--) asm volatile("nop");
while(x--) asm volatile("nop");
}
embedded-sw/boards/ml605/board.h
View file @ b139cd5a
......@@ -4,7 +4,7 @@
#include <hw/memlayout.h>
/****************************/
/* General Definitions */
/* General Definitions */
/****************************/
/* CPU Clock frequency in hertz */
#define CPU_CLOCK 100000000ULL
......
embedded-sw/dbe.vhd
View file @ b139cd5a
This diff is collapsed.
embedded-sw/dbe_main.c
View file @ b139cd5a
#include "gpio.h" // GPIO device funtions
#include "dma.h" // DMA device functions
#include "gpio.h" // GPIO device funtions
#include "dma.h" // DMA device functions
#include "fmc150.h" // FMC150 device functions
#include "uart.h" // UART device functions
#include "memmgr.h" // memory pool functions
#include "uart.h" // UART device functions
#include "memmgr.h" // memory pool functions
#include "board.h" // board definitions
/* Each loop iteration takes 4 cycles.
* It runs at 100MHz.
* Sleep 0.2 second.
/* Each loop iteration takes 4 cycles.
* It runs at 100MHz.
* Sleep 0.2 second.
*/
#define LED_DELAY (100000000/4/5)
......@@ -23,144 +23,144 @@ void _irq_entry(void){}
int dbe_init(void)
{
// Initialize memory pool
memmgr_init();
// Initialize memory pool
memmgr_init();
// Fill SDB device structures
sdb_find_devices();
// Fill SDB device structures
sdb_find_devices();
// Initialize specific components
if(uart_init() == -1)
return -1;
// Initialize specific components
if(uart_init() == -1)
return -1;
if(dma_init() == -1)
return -1;
if(dma_init() == -1)
return -1;
if(gpio_init() == -1)
return -1;
if(gpio_init() == -1)
return -1;
if(fmc150_init() == -1)
return -1;
if(fmc150_init() == -1)
return -1;
return 0;
return 0;
}
void print_header(void)
{
mprintf("-------------------------------------------\n");
mprintf("| DBE EXAMPLE APPLICATION |\n");
mprintf("| |\n");
mprintf("| This application aims to demostrate |\n");
mprintf("| the capabilities of the DBE project |\n");
mprintf("| DBE EXAMPLE APPLICATION |\n");
mprintf("| |\n");
mprintf("| This application aims to demostrate |\n");
mprintf("| the capabilities of the DBE project |\n");
mprintf("-------------------------------------------\n\n");
}
void memmgr_test(void)
{
/* Simple Memory Pool Test */
char *p = (char *)memmgr_alloc(100*sizeof(char));
mprintf("-------------------------------------------\n");
mprintf("| Memory pool test |\n");
/* Simple Memory Pool Test */
char *p = (char *)memmgr_alloc(100*sizeof(char));
mprintf("-------------------------------------------\n");
mprintf("| Memory pool test |\n");
mprintf("-------------------------------------------\n\n");
if(p){
strcpy(p, " Dynamic allocated string with memory pool\n\n");
mprintf(p);
mprintf(" Test passed!\n");
}
else
mprintf(" Test failed. Could not allocate memory!\n");
memmgr_print_stats();
memmgr_free(p);
if(p){
strcpy(p, " Dynamic allocated string with memory pool\n\n");
mprintf(p);
mprintf(" Test passed!\n");
}
else
mprintf(" Test failed. Could not allocate memory!\n");
memmgr_print_stats();
memmgr_free(p);
}
void leds_test(void)
{
/* Simple LEDs test */
int i, j;
/* Simple LEDs test */
int i, j;
mprintf("-------------------------------------------\n");
mprintf("| Leds test |\n");
mprintf("-------------------------------------------\n");
mprintf("| Leds test |\n");
mprintf("-------------------------------------------\n\n");
mprintf(" Testing LEDs...\n");
/* Rotate the LEDs */
for ( j = 0; j < NUM_LED_ITER; ++j)
for (i = 0; i < NUM_LEDS; ++i){
// Set led at position i
gpio_out(i, 1);
/* Each loop iteration takes 4 cycles.
* It runs at 100MHz.
* Sleep 0.2 second.
*/
delay(LED_DELAY);
// Clear led at position i
gpio_out(i, 0);
}
// End test with 4 leds set
gpio_out(0, 1);
gpio_out(2, 1);
gpio_out(4, 1);
gpio_out(6, 1);
mprintf(" Testing LEDs...\n");
/* Rotate the LEDs */
for ( j = 0; j < NUM_LED_ITER; ++j)
for (i = 0; i < NUM_LEDS; ++i){
// Set led at position i
gpio_out(i, 1);
/* Each loop iteration takes 4 cycles.
* It runs at 100MHz.
* Sleep 0.2 second.
*/
delay(LED_DELAY);
// Clear led at position i
gpio_out(i, 0);
}
// End test with 4 leds set
gpio_out(0, 1);
gpio_out(2, 1);
gpio_out(4, 1);
gpio_out(6, 1);
}
void fmc150_test()
{
mprintf("-------------------------------------------\n");
mprintf("| FMC150 test |\n");
mprintf("-------------------------------------------\n");
mprintf("| FMC150 test |\n");
mprintf("-------------------------------------------\n\n");
mprintf(" Testing FMC150 CDCE72010 regs...\n");
mprintf(" Testing FMC150 CDCE72010 regs...\n");
if (init_cdce72010() < 0){
mprintf(" Error initializing FMC150!\n");
return -1;
}
mprintf(" FMC150 CDCE72010 initialized\n");
if (init_cdce72010() < 0){
mprintf(" Error initializing FMC150!\n");
return -1;
}
mprintf(" FMC150 CDCE72010 initialized\n");
}
int main(void)
{
int i, j;
char *p;
// Board initialization
if(board_init() == -1)
return -1;
// General initialization
if(dbe_init() == -1){
mprintf(" Error initializing DBE Board! Exiting...\n");
return -1;
}
print_header();
/* It would be nice to employ a callback system. For this to work,
a hardware timer should be running with a wishbone interface
and a interrupt pin to LM32 processor */
/* Output memory layout */
char *p;
// Board initialization
if(board_init() == -1)
return -1;
// General initialization
if(dbe_init() == -1){
mprintf(" Error initializing DBE Board! Exiting...\n");
return -1;
}
print_header();
/* It would be nice to employ a callback system. For this to work,
a hardware timer should be running with a wishbone interface
and a interrupt pin to LM32 processor */
/* Output memory layout */
sdb_print_devices();
/* Test memory pool */
memmgr_test();
/* Test leds */
leds_test();
/* FMC150 test */
fmc150_test();
mprintf("-------------------------------------------\n");
mprintf(" End of the example application\n");
/* Test memory pool */
memmgr_test();
/* Test leds */
leds_test();
/* FMC150 test */
fmc150_test();
mprintf("-------------------------------------------\n");
mprintf(" End of the example application\n");
return 0;
}
embedded-sw/dev/dev.mk
View file @ b139cd5a
OBJS_DEV = dev/dma.o \
OBJS_DEV = dev/dma.o \
dev/fmc150.o \
dev/gpio.o \
dev/uart.o \
dev/sdb.o
dev/uart.o \
dev/sdb.o
embedded-sw/dev/dma.c
View file @ b139cd5a
#include "board.h" // Board definitions: DMA device structure
#include "dma.h" // DMA device functions
#include "board.h" // Board definitions: DMA device structure
#include "dma.h" // DMA device functions
// Global DMA handler.
dma_t *dma;
int dma_init(void)
{
if (dma_devl->devices){
//if (BASE_DMA){
// get first dma device found
dma = (dma_t *)dma_devl->devices->base;//BASE_DMA;
return 0;
}
return -1;
if (dma_devl->devices){
// get first dma device found
dma = (dma_t *)dma_devl->devices->base;//BASE_DMA;
return 0;
}
return -1;
}
/* DMA user interface definition */
int read_is_addr(void)
{
return dma->RD_ADDR;
return dma->RD_ADDR;
}
void write_is_addr(int addr)
{
dma->WR_ADDR = (uint32_t)addr;
dma->WR_ADDR = (uint32_t)addr;
}
int read_strd(void)
{
return dma->RD_STRD;
return dma->RD_STRD;
}
void write_strd(int strd)
{
dma->WR_STRD = (uint32_t) strd;
dma->WR_STRD = (uint32_t) strd;
}
int read_tr_count(void)
{
return dma->TR_COUNT;
}
return dma->TR_COUNT;
}
embedded-sw/dev/fmc150.c
View file @ b139cd5a
......@@ -58,7 +58,7 @@ uint32_t cdce72010_regs[CDCE72010_NUMREGS] = {
// DDS = 3.072MHz -> Phase increment = 2048d
0x682C0290,
0x68840041,
0x83860002, //divide by 5
0x83860002, //divide by 5
//0x83840002, //divide by 4
0x68400003,
0xE9800004,
......@@ -144,28 +144,27 @@ fmc150_t *fmc150;
int fmc150_init(void)
{
if (fmc150_devl->devices){
//if (BASE_FMC150){
// get first fmc150 device found
fmc150 = (fmc150_t *)fmc150_devl->devices->base;//BASE_FMC150;
return 0;
}
return -1;
if (fmc150_devl->devices){
// get first gpio device found
fmc150 = (fmc150_t *)fmc150_devl->devices->base;//BASE_FMC150;
return 0;
}
return -1;
}
void update_fmc150_adc_delay(uint8_t adc_strobe_delay, uint8_t adc_cha_delay, uint8_t adc_chb_delay)
{
fmc150->ADC_DLY = (uint32_t) FMC150_ADC_DLY_STR_W(adc_strobe_delay) +
fmc150->ADC_DLY = (uint32_t) FMC150_ADC_DLY_STR_W(adc_strobe_delay) +
(uint32_t) FMC150_ADC_DLY_CHA_W(adc_cha_delay) +
(uint32_t) FMC150_ADC_DLY_CHB_W(adc_chb_delay);
fmc150->FLGS_PULSE = 0x1;
fmc150->FLGS_PULSE = 0x1;
}
/* Check if 150 is busy */
int fmc150_spi_busy(void)
{
return fmc150->FLGS_OUT & FMC150_FLGS_OUT_SPI_BUSY;
return fmc150->FLGS_OUT & FMC150_FLGS_OUT_SPI_BUSY;
}
int read_fmc150_register(uint32_t cs, uint32_t addr, uint32_t* data)
......@@ -239,8 +238,8 @@ int init_cdce72010()
uint32_t reg;
/* Write regs to cdce72010 statically */
// Do not write the last register, as it is Read-only
for(i = 0; i < CDCE72010_NUMREGS; ++i){
// Do not write the last register, as it is Read-only
for(i = 0; i < CDCE72010_NUMREGS-1; ++i){
if(fmc150_spi_busy_loop() < 0){
dbg_print("init_cdce72010: max SPI tries excceded!\n");
return -1;
......@@ -248,27 +247,27 @@ int init_cdce72010()
dbg_print("init_cdce72010: writing data: 0x%x at register addr: 0x%x\n", cdce72010_regs[i], i);
// The CDCE72010 chip word addressed , hence the i
// The CDCE72010 chip word addressed , hence the "i" addressing index
write_fmc150_register(FMC150_CS_CDCE72010, i, cdce72010_regs[i]);
// Do a write-read cycle in order to ensure that we wrote the correct value
delay(SPI_DELAY);
delay(SPI_DELAY);
if(fmc150_spi_busy_loop() < 0){
dbg_print("init_cdce72010: max SPI tries excceded!\n");
return -1;
dbg_print("init_cdce72010: max SPI tries excceded!\n");
return -1;
}
// The CDCE72010 chip word addressed , hence the i
read_fmc150_register(FMC150_CS_CDCE72010, i, &reg);
dbg_print("init_cdce72010: reading data: 0x%x at register addr: 0x%x\n", reg, i);
// The CDCE72010 chip word addressed , hence the "i" addressing index
read_fmc150_register(FMC150_CS_CDCE72010, i, &reg);
dbg_print("init_cdce72010: reading data: 0x%x at register addr: 0x%x\n", reg, i);
// Check if value written is the same of the value just read
if(cdce72010_regs[i] != reg){
dbg_print("init_cdce72010: error: data written (0x%x) != data read (0x%x)!\n",
cdce72010_regs[i], reg);
return -1;
}
if(cdce72010_regs[i] != reg){
dbg_print("init_cdce72010: error: data written (0x%x) != data read (0x%x)!\n",
cdce72010_regs[i], reg);
return -1;
}
delay(SPI_DELAY);
}
......
embedded-sw/dev/gpio.c
View file @ b139cd5a
#include "board.h" // Board definitions: GPIO device structure
#include "gpio.h" // GPIO device functions
#include "board.h" // Board definitions: GPIO device structure
#include "gpio.h" // GPIO device functions
// Global GPIO handler.
gpio_t *gpio;
int gpio_init(void)
int gpio_init(gpio_t * gpio, int id)
{
if (gpio_devl->devices){
//if (BASE_GPIO){
// get first gpio device found
gpio = (gpio_t *)gpio_devl->devices->base;//BASE_GPIO;
return 0;
}
if (gpio_devl->devices){
// get first gpio device found
gpio = (gpio_t *)gpio_devl->devices->base;//BASE_GPIO;
return 0;
}
return -1;
return -1;
}
/* GPIO user interface definition */
......@@ -29,11 +28,11 @@ void gpio_dir(int pin, int val)
{
if(val)
gpio->DDR |= (1<<pin);
else
gpio->DDR &= ~(1<<pin);
else
gpio->DDR &= ~(1<<pin);
}
int gpio_in(int pin)
{
return gpio->PSR & (1<<pin) ? 1 : 0;
return gpio->PSR & (1<<pin) ? 1 : 0;
}
embedded-sw/dev/sdb.c
View file @ b139cd5a
#include "hw/memlayout.h"
#include "memmgr.h" // malloc clone (memory pool)
#include "memmgr.h" // malloc clone (memory pool)
#define SDB_INTERCONNET 0x00
#define SDB_DEVICE 0x01
#define SDB_BRIDGE 0x02
#define SDB_EMPTY 0xFF
#define SDB_DEVICE 0x01
#define SDB_BRIDGE 0x02
#define SDB_EMPTY 0xFF
typedef struct pair64 {
uint32_t high;
......@@ -60,7 +60,7 @@ typedef union sdb_record {
} sdb_record_t;
static unsigned char *find_device_deep(unsigned int base, unsigned int sdb,
unsigned int devid)
unsigned int devid)
{
sdb_record_t *record = (sdb_record_t *) sdb;
int records = record->interconnect.sdb_records;
......@@ -69,16 +69,16 @@ static unsigned char *find_device_deep(unsigned int base, unsigned int sdb,
for (i = 0; i < records; ++i, ++record) {
if (record->empty.record_type == SDB_BRIDGE) {
unsigned char *out =
find_device_deep(base +
record->bridge.sdb_component.
addr_first.low,
record->bridge.sdb_child.low,
devid);
find_device_deep(base +
record->bridge.sdb_component.
addr_first.low,
record->bridge.sdb_child.low,
devid);
if (out)
return out;
}
if (record->empty.record_type == SDB_DEVICE &&
record->device.sdb_component.product.device_id == devid) {
record->device.sdb_component.product.device_id == devid) {
break;
}
}
......@@ -91,53 +91,48 @@ static unsigned char *find_device_deep(unsigned int base, unsigned int sdb,
}
static void find_device_deep_all_rec(struct dev_node **dev, unsigned int base,
unsigned int sdb, unsigned int devid)
unsigned int sdb, unsigned int devid)
{
sdb_record_t *record = (sdb_record_t *) sdb;
sdb_record_t *record = (sdb_record_t *) sdb;
int records = record->interconnect.sdb_records;
int i;
// Number of devices found
//int devices_count = 0;
for (i = 0; i < records; ++i, ++record) {
if (record->empty.record_type == SDB_BRIDGE) {
find_device_deep_all_rec(dev, base +
record->bridge.sdb_component.
addr_first.low,
record->bridge.sdb_child.low,
devid);
//if (base_dev_addr)
// return base_dev_addr;
find_device_deep_all_rec(dev, base +
record->bridge.sdb_component.
addr_first.low,
record->bridge.sdb_child.low,
devid);
}
if (record->empty.record_type == SDB_DEVICE &&
record->device.sdb_component.product.device_id == devid) {
//break;
// Alloc new node device
*dev = (struct dev_node *)memmgr_alloc(sizeof(struct dev_node));
(*dev)->base = (unsigned char *)(base +
record->device.sdb_component.addr_first.low);
// Ensure a null pointer on end of list
(*dev)->next = 0;
// Pass new node address
dev = &(*dev)->next;
record->device.sdb_component.product.device_id == devid) {
// Alloc new node device
*dev = (struct dev_node *)memmgr_alloc(sizeof(struct dev_node));
(*dev)->base = (unsigned char *)(base +
record->device.sdb_component.addr_first.low);
// Ensure a null pointer on end of list
(*dev)->next = 0;
// Pass new node address
dev = &(*dev)->next;
}
}
}
static struct dev_list *find_device_deep_all(unsigned int base, unsigned int sdb,
unsigned int devid)
unsigned int devid)
{
// Device structure list
struct dev_list *dev = (struct dev_list *)memmgr_alloc(sizeof(struct dev_list));
// Device structure list
struct dev_list *dev = (struct dev_list *)memmgr_alloc(sizeof(struct dev_list));
// Initialize structure
dev->devid = devid;
dev->devices = 0;
// Initialize structure
dev->devid = devid;
dev->devices = 0;
// Fill device list with the appropriate nodes
find_device_deep_all_rec(&(dev->devices), base, sdb, devid);
// Fill device list with the appropriate nodes
find_device_deep_all_rec(&(dev->devices), base, sdb, devid);
return dev;
return dev;
}
static void print_devices_deep(unsigned int base, unsigned int sdb)
......@@ -150,9 +145,9 @@ static void print_devices_deep(unsigned int base, unsigned int sdb)
for (i = 0; i < records; ++i, ++record) {
if (record->empty.record_type == SDB_BRIDGE)
print_devices_deep(base +
record->bridge.sdb_component.
addr_first.low,
record->bridge.sdb_child.low);
record->bridge.sdb_component.
addr_first.low,
record->bridge.sdb_child.low);
if (record->empty.record_type != SDB_DEVICE)
continue;
......@@ -179,34 +174,25 @@ static struct dev_list *find_device_all(unsigned int devid)
void sdb_print_devices(void)
{
mprintf("-------------------------------------------\n");
mprintf("| SDB memory map |\n");
mprintf("-------------------------------------------\n");
mprintf("| SDB memory map |\n");
mprintf("-------------------------------------------\n\n");
print_devices_deep(0, SDB_ADDRESS);
}
void sdb_find_devices(void)
{
//BASE_DMA = find_device(0xcababa56);
//BASE_DMA = (unsigned char *)0x20000400;
//BASE_FMA150 = find_device(0xf8c150c1);
//BASE_FMA150 = (unsigned char *)0x20000500;
//BASE_UART = find_device(0x8a5719ae);
//BASE_UART = (unsigned char *)0x20000600;
//BASE_GPIO = find_device(0x35aa6b95);
//BASE_GPIO = (unsigned char *)0x20000700;
dma_devl = find_device_all(0xcababa56);
fmc150_devl = find_device_all(0xf8c150c1);
uart_devl = find_device_all(0x8a5719ae);
gpio_devl = find_device_all(0x35aa6b95);
//BASE_MINIC = find_device(0xab28633a);
//BASE_EP = find_device(0x650c2d4f);
//BASE_SOFTPLL = find_device(0x65158dc0);
//BASE_PPS_GEN = find_device(0xde0d8ced);
//BASE_SYSCON = find_device(0xff07fc47);
//BASE_UART = find_device(0xe2d13d04);
//BASE_ONEWIRE = find_device(0x779c5443);
//BASE_ETHERBONE_CFG = find_device(0x68202b22);
//BASE_DMA = find_device(0xcababa56);
//BASE_DMA = (unsigned char *)0x20000400;
//BASE_FMA150 = find_device(0xf8c150c1);
//BASE_FMA150 = (unsigned char *)0x20000500;
//BASE_UART = find_device(0x8a5719ae);
//BASE_UART = (unsigned char *)0x20000600;
//BASE_GPIO = find_device(0x35aa6b95);
//BASE_GPIO = (unsigned char *)0x20000700;
dma_devl = find_device_all(0xcababa56);
fmc150_devl = find_device_all(0xf8c150c1);
uart_devl = find_device_all(0x8a5719ae);
gpio_devl = find_device_all(0x35aa6b95);
}
embedded-sw/dev/uart.c
View file @ b139cd5a
#include <inttypes.h>
#include "board.h" // Board definitions: UART device structure
#include "uart.h" // UART device functions
#include "board.h" // Board definitions: UART device structure
#include "uart.h" // UART device functions
#define CALC_BAUD(baudrate) \
( ((( (unsigned long long)baudrate * 8ULL) << (16 - 7)) + \
(CPU_CLOCK >> 8)) / (CPU_CLOCK >> 7) )
( ((( (unsigned long long)baudrate * 8ULL) << (16 - 7)) + \
(CPU_CLOCK >> 8)) / (CPU_CLOCK >> 7) )
// Global UART handler.
uart_t *uart;
int uart_init(void)
{
if (uart_devl->devices){
//if (BASE_UART){
// get first uart device found
uart = (uart_t *)uart_devl->devices->base;//BASE_UART;
uart->BCR = CALC_BAUD(UART_BAUDRATE);
return 0;
}
// return error in case none uart device found
return -1;
if (uart_devl->devices){
// get first uart device found
uart = (uart_t *)uart_devl->devices->base;//BASE_UART;
uart->BCR = CALC_BAUD(UART_BAUDRATE);
return 0;
}
// return error in case none uart device found
return -1;
}
void uart_write_byte(int b)
......
embedded-sw/include/util.c → embedded-sw/dev/util.c
View file @ b139cd5a
......@@ -16,15 +16,15 @@
/* cut from libc sources */
#define YEAR0 1900
#define EPOCH_YR 1970
#define SECS_DAY (24L * 60L * 60L)
#define LEAPYEAR(year) (!((year) % 4) && (((year) % 100) || !((year) % 400)))
#define YEARSIZE(year) (LEAPYEAR(year) ? 366 : 365)
#define FIRSTSUNDAY(timp) (((timp)->tm_yday - (timp)->tm_wday + 420) % 7)
#define FIRSTDAYOF(timp) (((timp)->tm_wday - (timp)->tm_yday + 420) % 7)
#define TIME_MAX ULONG_MAX
#define ABB_LEN 3
#define YEAR0 1900
#define EPOCH_YR 1970
#define SECS_DAY (24L * 60L * 60L)
#define LEAPYEAR(year) (!((year) % 4) && (((year) % 100) || !((year) % 400)))
#define YEARSIZE(year) (LEAPYEAR(year) ? 366 : 365)
#define FIRSTSUNDAY(timp) (((timp)->tm_yday - (timp)->tm_wday + 420) % 7)
#define FIRSTDAYOF(timp) (((timp)->tm_wday - (timp)->tm_yday + 420) % 7)
#define TIME_MAX ULONG_MAX
#define ABB_LEN 3
static const char *_days[] = {
"Sun", "Mon", "Tue", "Wed",
......
embedded-sw/include/dma.h
View file @ b139cd5a
......@@ -3,17 +3,17 @@
#include "inttypes.h"
/*
/*
This structure must conform to what it is specified in the
FPGA software-acessible registers. See general-cores/cores/wishbone/wb_dma.vhd
*/
struct DMA_WB
{
uint32_t RD_ADDR; /* Read issue address register */
uint32_t WR_ADDR; /* Write issue address register */
uint32_t RD_STRD; /* Read stride */
uint32_t WR_STRD; /* Write stride */
uint32_t TR_COUNT; /* Transfer count */
uint32_t RD_ADDR; /* Read issue address register */
uint32_t WR_ADDR; /* Write issue address register */
uint32_t RD_STRD; /* Read stride */
uint32_t WR_STRD; /* Write stride */
uint32_t TR_COUNT; /* Transfer count */
};
typedef volatile struct DMA_WB dma_t;
......@@ -25,6 +25,6 @@ void write_is_addr(int addr);
int read_strd(void);
void write_strd(int strd);
int read_tr_count(void);
#endif
embedded-sw/include/fmc150.h
View file @ b139cd5a
......@@ -7,7 +7,7 @@
#ifdef FMC150_DEBUG
#define dbg_print(fmt, args...) mprintf(fmt, ## args)
#else
#define dbg_print(fmt, args...) /* Don't do anything in release builds */
#define dbg_print(fmt, args...) /* Don't do anything in release builds */
#endif
// Number of CDCE72010 registers
......@@ -26,6 +26,6 @@ int fmc150_spi_busy(void);
void update_fmc150_adc_delay(uint8_t adc_strobe_delay, uint8_t adc_cha_delay, uint8_t adc_chb_delay);
int read_fmc150_register(uint32_t cs, uint32_t addr, uint32_t* data);
int write_fmc150_register(uint32_t cs, uint32_t addr, uint32_t data);
#endif
embedded-sw/include/gpio.h
View file @ b139cd5a
......@@ -3,16 +3,16 @@
#include "inttypes.h"
/*
/*
This structure must conform to what it is specified in the
FPGA software-acessible registers. See general-cores/cores/wishbone/wb_gpio_port.vhd
*/
struct GPIO_WB
{
uint32_t CODR; /* Clear output register */
uint32_t SODR; /* Set output register */
uint32_t DDR; /* Data direction register (1 means out) */
uint32_t PSR; /* Pin state register */
uint32_t CODR; /* Clear output register */
uint32_t SODR; /* Set output register */
uint32_t DDR; /* Data direction register (1 means out) */
uint32_t PSR; /* Pin state register */
};
typedef volatile struct GPIO_WB gpio_t;
......@@ -23,6 +23,6 @@ int gpio_init(void);
void gpio_out(int pin, int val);
void gpio_dir(int pin, int val);
int gpio_in(int pin);
#endif
embedded-sw/include/hw/etherbone-config.h
View file @ b139cd5a
......@@ -2,15 +2,15 @@
#define ETHERBONE_CONFIG
/* These values are taken directly from the Etherbone specification */
#define ERROR_STATUS_HIGH 0
#define ERROR_STATUS_LOW 4
#define SDB_ADDRESS_HIGH 8
#define SDB_ADDRSES_LOW 12
#define ERROR_STATUS_HIGH 0
#define ERROR_STATUS_LOW 4
#define SDB_ADDRESS_HIGH 8
#define SDB_ADDRSES_LOW 12
/* These are implementation specific */
#define EB_MAC_HIGH16 16
#define EB_MAC_LOW32 20
#define EB_IPV4 24
#define EB_PORT 28
#define EB_MAC_HIGH16 16
#define EB_MAC_LOW32 20
#define EB_IPV4 24
#define EB_PORT 28
#endif
embedded-sw/include/hw/memlayout.h
View file @ b139cd5a
......@@ -10,19 +10,19 @@
//#define NUM_GPIO_DEVS 2
/* Simple device nodes for supporting various instances
of the same component */
of the same component */
struct dev_node{
unsigned char *base;
struct dev_node *next;
unsigned char *base;
struct dev_node *next;
};
/* List of devices of the same kind (same devid).
Note the use of flexible array member. Space is allocated
only when instanciated */
Note the use of flexible array member. Space is allocated
only when instanciated */
struct dev_list{
unsigned int devid;
//unsigned int size;
struct dev_node *devices;
unsigned int devid;
//unsigned int size;
struct dev_node *devices;
};
/* Automate the address peripheral discover. use SDB */
......@@ -44,7 +44,7 @@ void sdb_find_devices(void);
void sdb_print_devices(void);
/*************************/
/* Base addresses */
/* Base addresses */
/*************************/
/* RAM Definitions */
......
embedded-sw/include/hw/wb_fmc150.h
View file @ b139cd5a
/*
Register definitions for slave core: FMC ADC/DAC interface registers
Register definitions for slave core: FMC ADC/DAC interface registers
* File : wb_fmc150.h
* Author : auto-generated by wbgen2 from xfmc150.wb
* Created : Thu Oct 11 10:21:39 2012
* Standard : ANSI C
* File : wb_fmc150.h
* Author : auto-generated by wbgen2 from xfmc150.wb
* Created : Thu Oct 11 10:21:39 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
......@@ -36,10 +36,10 @@
/* definitions for register: Input Flags for FMC150 */
/* definitions for field: SPI Read/Write flag in reg: Input Flags for FMC150 */
#define FMC150_FLGS_IN_SPI_RW WBGEN2_GEN_MASK(0, 1)
#define FMC150_FLGS_IN_SPI_RW WBGEN2_GEN_MASK(0, 1)
/* definitions for field: External Clock for ADC in reg: Input Flags for FMC150 */
#define FMC150_FLGS_IN_EXT_CLK WBGEN2_GEN_MASK(1, 1)
#define FMC150_FLGS_IN_EXT_CLK WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Address for Chips on FMC150 */
......@@ -48,70 +48,70 @@
/* definitions for register: Chipselect for Chips on FMC150 */
/* definitions for field: Chipselect for cdce72010 in reg: Chipselect for Chips on FMC150 */
#define FMC150_CS_CDCE72010 WBGEN2_GEN_MASK(0, 1)
#define FMC150_CS_CDCE72010 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Chipselect for ads62p49 in reg: Chipselect for Chips on FMC150 */
#define FMC150_CS_ADS62P49 WBGEN2_GEN_MASK(1, 1)
#define FMC150_CS_ADS62P49 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Chipselect for dac3283 in reg: Chipselect for Chips on FMC150 */
#define FMC150_CS_DAC3283 WBGEN2_GEN_MASK(2, 1)
#define FMC150_CS_DAC3283 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Chipselect for amc7823 in reg: Chipselect for Chips on FMC150 */
#define FMC150_CS_AMC7823 WBGEN2_GEN_MASK(3, 1)
#define FMC150_CS_AMC7823 WBGEN2_GEN_MASK(3, 1)
/* definitions for register: ADC Delay */
/* definitions for field: ADC Strobe delay in reg: ADC Delay */
#define FMC150_ADC_DLY_STR_MASK WBGEN2_GEN_MASK(0, 5)
#define FMC150_ADC_DLY_STR_SHIFT 0
#define FMC150_ADC_DLY_STR_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define FMC150_ADC_DLY_STR_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
#define FMC150_ADC_DLY_STR_MASK WBGEN2_GEN_MASK(0, 5)
#define FMC150_ADC_DLY_STR_SHIFT 0
#define FMC150_ADC_DLY_STR_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define FMC150_ADC_DLY_STR_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: ADC Channel A delay in reg: ADC Delay */
#define FMC150_ADC_DLY_CHA_MASK WBGEN2_GEN_MASK(8, 5)
#define FMC150_ADC_DLY_CHA_SHIFT 8
#define FMC150_ADC_DLY_CHA_W(value) WBGEN2_GEN_WRITE(value, 8, 5)
#define FMC150_ADC_DLY_CHA_R(reg) WBGEN2_GEN_READ(reg, 8, 5)
#define FMC150_ADC_DLY_CHA_MASK WBGEN2_GEN_MASK(8, 5)
#define FMC150_ADC_DLY_CHA_SHIFT 8
#define FMC150_ADC_DLY_CHA_W(value) WBGEN2_GEN_WRITE(value, 8, 5)
#define FMC150_ADC_DLY_CHA_R(reg) WBGEN2_GEN_READ(reg, 8, 5)
/* definitions for field: ADC Strobe delay in reg: ADC Delay */
#define FMC150_ADC_DLY_CHB_MASK WBGEN2_GEN_MASK(16, 5)
#define FMC150_ADC_DLY_CHB_SHIFT 16
#define FMC150_ADC_DLY_CHB_W(value) WBGEN2_GEN_WRITE(value, 16, 5)
#define FMC150_ADC_DLY_CHB_R(reg) WBGEN2_GEN_READ(reg, 16, 5)
#define FMC150_ADC_DLY_CHB_MASK WBGEN2_GEN_MASK(16, 5)
#define FMC150_ADC_DLY_CHB_SHIFT 16
#define FMC150_ADC_DLY_CHB_W(value) WBGEN2_GEN_WRITE(value, 16, 5)
#define FMC150_ADC_DLY_CHB_R(reg) WBGEN2_GEN_READ(reg, 16, 5)
/* definitions for register: Data Out From Chips on FMC150 */
/* definitions for register: Flags out from Chips on FMC150 */
/* definitions for field: SPI Busy in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_SPI_BUSY WBGEN2_GEN_MASK(0, 1)
#define FMC150_FLGS_OUT_SPI_BUSY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: CDCE72010 PLL Status in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_PLL_STATUS WBGEN2_GEN_MASK(1, 1)
#define FMC150_FLGS_OUT_PLL_STATUS WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FPGA ADC clock locked in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_ADC_CLK_LOCKED WBGEN2_GEN_MASK(2, 1)
#define FMC150_FLGS_OUT_ADC_CLK_LOCKED WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC present in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_FMC_PRST WBGEN2_GEN_MASK(3, 1)
#define FMC150_FLGS_OUT_FMC_PRST WBGEN2_GEN_MASK(3, 1)
PACKED struct FMC150_WB {
/* [0x0]: REG Input Flags for Pulsing Registers */
uint32_t FLGS_PULSE;
/* [0x4]: REG Input Flags for FMC150 */
uint32_t FLGS_IN;
/* [0x8]: REG Address for Chips on FMC150 */
uint32_t ADDR;
/* [0xc]: REG Data In for Chips on FMC150 */
uint32_t DATA_IN;
/* [0x10]: REG Chipselect for Chips on FMC150 */
uint32_t CS;
/* [0x14]: REG ADC Delay */
uint32_t ADC_DLY;
/* [0x18]: REG Data Out From Chips on FMC150 */
uint32_t DATA_OUT;
/* [0x1c]: REG Flags out from Chips on FMC150 */
uint32_t FLGS_OUT;
/* [0x0]: REG Input Flags for Pulsing Registers */
uint32_t FLGS_PULSE;
/* [0x4]: REG Input Flags for FMC150 */
uint32_t FLGS_IN;
/* [0x8]: REG Address for Chips on FMC150 */
uint32_t ADDR;
/* [0xc]: REG Data In for Chips on FMC150 */
uint32_t DATA_IN;
/* [0x10]: REG Chipselect for Chips on FMC150 */
uint32_t CS;
/* [0x14]: REG ADC Delay */
uint32_t ADC_DLY;
/* [0x18]: REG Data Out From Chips on FMC150 */
uint32_t DATA_OUT;
/* [0x1c]: REG Flags out from Chips on FMC150 */
uint32_t FLGS_OUT;
};
#endif
embedded-sw/include/hw/wb_uart.h
View file @ b139cd5a
/*
Register definitions for slave core: Simple Wishbone UART
Register definitions for slave core: Simple Wishbone UART
* File : ../../../../software/include/hw/wb_uart.h
* Author : auto-generated by wbgen2 from uart.wb
* Created : Mon Feb 21 22:25:02 2011
* Standard : ANSI C
* File : ../../../../software/include/hw/wb_uart.h
* Author : auto-generated by wbgen2 from uart.wb
* Created : Mon Feb 21 22:25:02 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE uart.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE uart.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
......@@ -33,28 +33,28 @@
/* definitions for register: Status Register */
/* definitions for field: TX busy in reg: Status Register */
#define UART_SR_TX_BUSY WBGEN2_GEN_MASK(0, 1)
#define UART_SR_TX_BUSY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX ready in reg: Status Register */
#define UART_SR_RX_RDY WBGEN2_GEN_MASK(1, 1)
#define UART_SR_RX_RDY WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Baudrate control register */
/* definitions for register: Transmit data regsiter */
/* definitions for field: Transmit data in reg: Transmit data regsiter */
#define UART_TDR_TX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_TDR_TX_DATA_SHIFT 0
#define UART_TDR_TX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_TDR_TX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
#define UART_TDR_TX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_TDR_TX_DATA_SHIFT 0
#define UART_TDR_TX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_TDR_TX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: Receive data regsiter */
/* definitions for field: Received data in reg: Receive data regsiter */
#define UART_RDR_RX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_RDR_RX_DATA_SHIFT 0
#define UART_RDR_RX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_RDR_RX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
#define UART_RDR_RX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_RDR_RX_DATA_SHIFT 0
#define UART_RDR_RX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_RDR_RX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* [0x0]: REG Status Register */
#define UART_REG_SR 0x00000000
/* [0x4]: REG Baudrate control register */
......
embedded-sw/include/hw/wb_vuart.h
View file @ b139cd5a
/*
Register definitions for slave core: Virtual UART
Register definitions for slave core: Virtual UART
* File : wb_vuart.h
* Author : auto-generated by wbgen2 from wb_virtual_uart.wb
* Created : Wed Apr 6 23:02:01 2011
* Standard : ANSI C
* File : wb_vuart.h
* Author : auto-generated by wbgen2 from wb_virtual_uart.wb
* Created : Wed Apr 6 23:02:01 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_virtual_uart.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_virtual_uart.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
......@@ -33,50 +33,50 @@
/* definitions for register: Status Register */
/* definitions for field: TX busy in reg: Status Register */
#define UART_SR_TX_BUSY WBGEN2_GEN_MASK(0, 1)
#define UART_SR_TX_BUSY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX ready in reg: Status Register */
#define UART_SR_RX_RDY WBGEN2_GEN_MASK(1, 1)
#define UART_SR_RX_RDY WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Baudrate control register */
/* definitions for register: Transmit data regsiter */
/* definitions for field: Transmit data in reg: Transmit data regsiter */
#define UART_TDR_TX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_TDR_TX_DATA_SHIFT 0
#define UART_TDR_TX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_TDR_TX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
#define UART_TDR_TX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_TDR_TX_DATA_SHIFT 0
#define UART_TDR_TX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_TDR_TX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: Receive data regsiter */
/* definitions for field: Received data in reg: Receive data regsiter */
#define UART_RDR_RX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_RDR_RX_DATA_SHIFT 0
#define UART_RDR_RX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_RDR_RX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
#define UART_RDR_RX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_RDR_RX_DATA_SHIFT 0
#define UART_RDR_RX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_RDR_RX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: FIFO 'UART TX FIFO' data output register 0 */
/* definitions for field: Char sent by UART to TX in reg: FIFO 'UART TX FIFO' data output register 0 */
#define UART_DEBUG_R0_TX_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_DEBUG_R0_TX_SHIFT 0
#define UART_DEBUG_R0_TX_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_DEBUG_R0_TX_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
#define UART_DEBUG_R0_TX_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_DEBUG_R0_TX_SHIFT 0
#define UART_DEBUG_R0_TX_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_DEBUG_R0_TX_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: FIFO 'UART TX FIFO' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'UART TX FIFO' control/status register */
#define UART_DEBUG_CSR_FULL WBGEN2_GEN_MASK(16, 1)
#define UART_DEBUG_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'UART TX FIFO' control/status register */
#define UART_DEBUG_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
#define UART_DEBUG_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'UART TX FIFO' control/status register */
#define UART_DEBUG_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_DEBUG_CSR_USEDW_SHIFT 0
#define UART_DEBUG_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_DEBUG_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
#define UART_DEBUG_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_DEBUG_CSR_USEDW_SHIFT 0
#define UART_DEBUG_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_DEBUG_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
PACKED struct UART_WB {
/* [0x0]: REG Status Register */
......
embedded-sw/include/memmgr/memmgr.h
View file @ b139cd5a
......@@ -2,7 +2,7 @@
// Statically-allocated memory manager
//
// by Eli Bendersky (eliben@gmail.com)
//
//
// This code is in the public domain.
//----------------------------------------------------------------
// Modified by Lucas Russo <lucas.russo@lnls.br>
......@@ -30,41 +30,41 @@
// memory manager:
//
// DEBUG_MEMMGR_FATAL
// Allow printing out a message when allocations fail
// Allow printing out a message when allocations fail
//
// DEBUG_MEMMGR_SUPPORT_STATS
// Allow printing out of stats in function
// memmgr_print_stats When this is disabled,
// memmgr_print_stats does nothing.
// Allow printing out of stats in function
// memmgr_print_stats When this is disabled,
// memmgr_print_stats does nothing.
//
// Note that in production code on an embedded system
// you'll probably want to keep those undefined, because
// they cause printf to be called.
//
// POOL_SIZE
// Size of the pool for new allocations. This is
// effectively the heap size of the application, and can
// be changed in accordance with the available memory
// resources.
// Size of the pool for new allocations. This is
// effectively the heap size of the application, and can
// be changed in accordance with the available memory
// resources.
//
// MIN_POOL_ALLOC_QUANTAS
// Internally, the memory manager allocates memory in
// quantas roughly the size of two ulong objects. To
// minimize pool fragmentation in case of multiple allocations
// and deallocations, it is advisable to not allocate
// blocks that are too small.
// This flag sets the minimal ammount of quantas for
// an allocation. If the size of a ulong is 4 and you
// set this flag to 16, the minimal size of an allocation
// will be 4 * 2 * 16 = 128 bytes
// If you have a lot of small allocations, keep this value
// low to conserve memory. If you have mostly large
// allocations, it is best to make it higher, to avoid
// fragmentation.
// Internally, the memory manager allocates memory in
// quantas roughly the size of two ulong objects. To
// minimize pool fragmentation in case of multiple allocations
// and deallocations, it is advisable to not allocate
// blocks that are too small.
// This flag sets the minimal ammount of quantas for
// an allocation. If the size of a ulong is 4 and you
// set this flag to 16, the minimal size of an allocation
// will be 4 * 2 * 16 = 128 bytes
// If you have a lot of small allocations, keep this value
// low to conserve memory. If you have mostly large
// allocations, it is best to make it higher, to avoid
// fragmentation.
//
// Notes:
// 1. This memory manager is *not thread safe*. Use it only
// for single thread/task applications.
// for single thread/task applications.
//
//#ifndef DEBUG_MEMMGR_FATAL
......
embedded-sw/lib/arp.c
View file @ b139cd5a
......@@ -28,7 +28,7 @@ void arp_init(const char *if_name)
saddr.family = PTPD_SOCK_RAW_ETHERNET;
arp_socket = ptpd_netif_create_socket(PTPD_SOCK_RAW_ETHERNET,
0, &saddr);
0, &saddr);
}
static int process_arp(uint8_t * buf, int len)
......@@ -43,7 +43,7 @@ static int process_arp(uint8_t * buf, int len)
/* Is it ARP request targetting our IP? */
getIP(myIP);
if (buf[ARP_OPER + 0] != 0 ||
buf[ARP_OPER + 1] != 1 || memcmp(buf + ARP_TPA, myIP, 4))
buf[ARP_OPER + 1] != 1 || memcmp(buf + ARP_TPA, myIP, 4))
return 0;
memcpy(hisMAC, buf + ARP_SHA, 6);
......@@ -82,7 +82,7 @@ void arp_poll(void)
return; /* can't do ARP w/o an address... */
if ((len = ptpd_netif_recvfrom(arp_socket,
&addr, buf, sizeof(buf), 0)) > 0)
&addr, buf, sizeof(buf), 0)) > 0)
if ((len = process_arp(buf, len)) > 0)
ptpd_netif_sendto(arp_socket, &addr, buf, len, 0);
}
embedded-sw/lib/bootp.c
View file @ b139cd5a
......@@ -94,8 +94,8 @@ int send_bootp(uint8_t * buf, int retry)
buf[UDP_CHECKSUM + 1] = 0;
sum =
ipv4_checksum((unsigned short *)(buf + UDP_VIRT_SADDR),
(BOOTP_END - UDP_VIRT_SADDR) / 2);
ipv4_checksum((unsigned short *)(buf + UDP_VIRT_SADDR),
(BOOTP_END - UDP_VIRT_SADDR) / 2);
if (sum == 0)
sum = 0xFFFF;
......@@ -119,8 +119,8 @@ int send_bootp(uint8_t * buf, int retry)
memset(buf + IP_DEST, 0xFF, 4);
sum =
ipv4_checksum((unsigned short *)(buf + IP_VERSION),
(IP_END - IP_VERSION) / 2);
ipv4_checksum((unsigned short *)(buf + IP_VERSION),
(IP_END - IP_VERSION) / 2);
buf[IP_CHECKSUM + 0] = sum >> 8;
buf[IP_CHECKSUM + 1] = sum & 0xff;
......@@ -141,8 +141,8 @@ int process_bootp(uint8_t * buf, int len)
return 0;
if (buf[IP_PROTOCOL] != 17 ||
buf[UDP_DPORT] != 0 || buf[UDP_DPORT + 1] != 68 ||
buf[UDP_SPORT] != 0 || buf[UDP_SPORT + 1] != 67)
buf[UDP_DPORT] != 0 || buf[UDP_DPORT + 1] != 68 ||
buf[UDP_SPORT] != 0 || buf[UDP_SPORT + 1] != 67)
return 0;
if (memcmp(buf + BOOTP_CHADDR, mac, 6))
......
embedded-sw/lib/icmp.c
View file @ b139cd5a
......@@ -68,8 +68,8 @@ int process_icmp(uint8_t * buf, int len)
// No need to copy payload; we modified things in-place
sum =
ipv4_checksum((unsigned short *)(buf + ICMP_TYPE),
(hisBodyLen + 4 + 1) / 2);
ipv4_checksum((unsigned short *)(buf + ICMP_TYPE),
(hisBodyLen + 4 + 1) / 2);
buf[ICMP_CHECKSUM + 0] = sum >> 8;
buf[ICMP_CHECKSUM + 1] = sum & 0xff;
......
embedded-sw/lib/ipv4.c
View file @ b139cd5a
......@@ -37,7 +37,7 @@ void ipv4_init(const char *if_name)
saddr.family = PTPD_SOCK_RAW_ETHERNET;
ipv4_socket = ptpd_netif_create_socket(PTPD_SOCK_RAW_ETHERNET,
0, &saddr);
0, &saddr);
}
static int bootp_retry = 0;
......@@ -50,7 +50,7 @@ void ipv4_poll(void)
int len;
if ((len = ptpd_netif_recvfrom(ipv4_socket, &addr,
buf, sizeof(buf), 0)) > 0) {
buf, sizeof(buf), 0)) > 0) {
if (needIP)
process_bootp(buf, len - 14);
......@@ -78,7 +78,7 @@ void getIP(unsigned char *IP)
void setIP(unsigned char *IP)
{
volatile unsigned int *eb_ip =
(unsigned int *)(BASE_ETHERBONE_CFG + EB_IPV4);
(unsigned int *)(BASE_ETHERBONE_CFG + EB_IPV4);
unsigned int ip;
memcpy(myIP, IP, 4);
......
embedded-sw/lib/memmgr/memmgr.c
View file @ b139cd5a
This diff is collapsed.
embedded-sw/lib/mprintf.c
View file @ b139cd5a
......@@ -196,8 +196,8 @@ CONVERSION_LOOP:
} while (u_val > 0);
// while (width--)
// *--ptr = fill;
// while (width--)
// *--ptr = fill;
while (*ptr)
*dst++ = *ptr++;
......
embedded-sw/lib/util.c
View file @ b139cd5a
......@@ -7,15 +7,15 @@
/* cut from libc sources */
#define YEAR0 1900
#define EPOCH_YR 1970
#define SECS_DAY (24L * 60L * 60L)
#define LEAPYEAR(year) (!((year) % 4) && (((year) % 100) || !((year) % 400)))
#define YEARSIZE(year) (LEAPYEAR(year) ? 366 : 365)
#define FIRSTSUNDAY(timp) (((timp)->tm_yday - (timp)->tm_wday + 420) % 7)
#define FIRSTDAYOF(timp) (((timp)->tm_wday - (timp)->tm_yday + 420) % 7)
#define TIME_MAX ULONG_MAX
#define ABB_LEN 3
#define YEAR0 1900
#define EPOCH_YR 1970
#define SECS_DAY (24L * 60L * 60L)
#define LEAPYEAR(year) (!((year) % 4) && (((year) % 100) || !((year) % 400)))
#define YEARSIZE(year) (LEAPYEAR(year) ? 366 : 365)
#define FIRSTSUNDAY(timp) (((timp)->tm_yday - (timp)->tm_wday + 420) % 7)
#define FIRSTDAYOF(timp) (((timp)->tm_wday - (timp)->tm_yday + 420) % 7)
#define TIME_MAX ULONG_MAX
#define ABB_LEN 3
static const char *_days[] = {
"Sun", "Mon", "Tue", "Wed",
......
embedded-sw/tools/genraminit.c
View file @ b139cd5a
......@@ -18,7 +18,7 @@ int main(int argc, char *argv[])
while (!feof(f)) {
fread(x, 1, 4, f);
printf("write %x %02X%02X%02X%02X\n", i++, x[0], x[1], x[2],
x[3]);
x[3]);
}
for (; i < n;) {
......
embedded-sw/tools/genramvhd.c
View file @ b139cd5a
......@@ -17,17 +17,17 @@ void help()
fprintf(stderr, "Usage: %s [OPTION] <filename>\n", program);
fprintf(stderr, "\n");
fprintf(stderr,
" -w <width> width of values in bytes [1/2/4/8/16] (4)\n");
" -w <width> width of values in bytes [1/2/4/8/16] (4)\n");
fprintf(stderr,
" -p <package> name of the output package (filename)\n");
" -p <package> name of the output package (filename)\n");
fprintf(stderr,
" -s <size> pad the output up to size bytes (filesize)\n");
" -s <size> pad the output up to size bytes (filesize)\n");
fprintf(stderr,
" -b big-endian operation (*)\n");
" -b big-endian operation (*)\n");
fprintf(stderr,
" -l little-endian operation \n");
fprintf(stderr, " -v verbose operation\n");
fprintf(stderr, " -h display this help and exit\n");
" -l little-endian operation \n");
fprintf(stderr, " -v verbose operation\n");
fprintf(stderr, " -h display this help and exit\n");
fprintf(stderr, "\n");
fprintf(stderr,
"Report Etherbone bugs to <white-rabbit-dev@ohwr.org>\n");
......@@ -67,8 +67,8 @@ int main(int argc, char **argv)
case 'w':
width = strtol(optarg, &value_end, 0);
if (*value_end || /* bad integer */
((width - 1) & width) != 0 || /* not a power of 2 */
width == 0 || width > 16) {
((width - 1) & width) != 0 || /* not a power of 2 */
width == 0 || width > 16) {
fprintf(stderr,
"%s: invalid value width -- '%s'\n",
program, optarg);
......@@ -214,7 +214,7 @@ int main(int argc, char **argv)
columns = 76 / entry_width;
printf("-- AUTOGENERATED FILE (from genramvhd.c run on %s) --\n",
argv[1]);
argv[1]);
printf("library IEEE;\n");
printf("use IEEE.std_logic_1164.all;\n");
printf("use IEEE.numeric_std.all;\n");
......@@ -225,12 +225,12 @@ int main(int argc, char **argv)
printf("package %s_pkg is\n", package);
printf
(" constant %s_init : t_meminit_array(%ld downto 0, %ld downto 0) := (\n",
package, size - 1, (width * 8) - 1);
(" constant %s_init : t_meminit_array(%ld downto 0, %ld downto 0) := (\n",
package, size - 1, (width * 8) - 1);
for (i = 0; i < size; ++i) {
if (i % columns == 0)
printf(" ");
printf(" ");
if (i < elements) {
if (fread(x, 1, width, f) != width) {
......
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