hdl/top/ml_605/*_dsp_fmc130m_4ch/*: debug port mapping

Now, we have the FPGA deswitching clock output to a SMA conector (for debug)

hdl/top/ml_605/_dsp_fmc130m_4ch/: debug port mapping
Now, we have the FPGA deswitching clock output to a SMA conector (for debug)
afa6ad43 · Lucas Russo · 30ab04da · afa6ad43
Commit afa6ad43 authored Mar 21, 2014 by Lucas Russo
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dbe_bpm_dsp.vhd hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd +4 -2

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--- a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd
+++ b/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd
@@ -2076,6 +2076,8 @@ begin
    -- Output to RFFE board
    -----------------------------
    clk_swap_o                              => clk_rffe_swap,
+    flag1_o                                 => flag1_int,
+    flag2_o                                 => flag2_int,
    ctrl1_o                                 => open,
    ctrl2_o                                 => open,
@@ -2176,8 +2178,8 @@ begin
  --dsp_ksum                                  <= "10000000000000000000000000"; -- 1.0 FIX26_25
  --flag1_int                                 <= fs_clk;
-  flag1_int                                 <= dsp_clk_ce_35;     -- FIXME!!
+  --flag1_int                                 <= dsp_clk_ce_35;     -- FIXME!!
-  flag2_int                                 <= dsp_clk_ce_70;     -- FIXME!!
+  --flag2_int                                 <= dsp_clk_ce_70;     -- FIXME!!
  flag1_o                                   <= flag1_int;
  flag2_o                                   <= flag2_int;