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Commit 9e636a5e authored by Lucas Russo's avatar Lucas Russo
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modules/*/wb_acq_core/*: remove unused/old regs file

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hdl/modules/dbe_wishbone/wb_acq_core/wbgen/wb_acq_core_regs_defs.h deleted 100644 → 0
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/*
Register definitions for slave core: BPM FSM Acquisition registers
* File : wb_acq_core_regs_defs.h
* Author : auto-generated by wbgen2 from acq_core.wb
* Created : Thu Dec 5 09:08:25 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE acq_core.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_ACQ_CORE_WB
#define __WBGEN2_REGDEFS_ACQ_CORE_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control register */
/* definitions for field: State machine acquisition_start command (ignore on read) in reg: Control register */
#define ACQ_CORE_CTL_FSM_START_ACQ WBGEN2_GEN_MASK(0, 1)
/* definitions for field: State machine stop command (ignore on read) in reg: Control register */
#define ACQ_CORE_CTL_FSM_STOP_ACQ WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reserved1 in reg: Control register */
#define ACQ_CORE_CTL_RESERVED1_MASK WBGEN2_GEN_MASK(2, 14)
#define ACQ_CORE_CTL_RESERVED1_SHIFT 2
#define ACQ_CORE_CTL_RESERVED1_W(value) WBGEN2_GEN_WRITE(value, 2, 14)
#define ACQ_CORE_CTL_RESERVED1_R(reg) WBGEN2_GEN_READ(reg, 2, 14)
/* definitions for field: Acquire data immediately and don't wait for any trigger (ignore on read) in reg: Control register */
#define ACQ_CORE_CTL_FSM_ACQ_NOW WBGEN2_GEN_MASK(16, 1)
/* definitions for field: Reserved2 in reg: Control register */
#define ACQ_CORE_CTL_RESERVED2_MASK WBGEN2_GEN_MASK(17, 15)
#define ACQ_CORE_CTL_RESERVED2_SHIFT 17
#define ACQ_CORE_CTL_RESERVED2_W(value) WBGEN2_GEN_WRITE(value, 17, 15)
#define ACQ_CORE_CTL_RESERVED2_R(reg) WBGEN2_GEN_READ(reg, 17, 15)
/* definitions for register: Status register */
/* definitions for field: State machine status in reg: Status register */
#define ACQ_CORE_STA_FSM_STATE_MASK WBGEN2_GEN_MASK(0, 3)
#define ACQ_CORE_STA_FSM_STATE_SHIFT 0
#define ACQ_CORE_STA_FSM_STATE_W(value) WBGEN2_GEN_WRITE(value, 0, 3)
#define ACQ_CORE_STA_FSM_STATE_R(reg) WBGEN2_GEN_READ(reg, 0, 3)
/* definitions for field: FSM acquisition status in reg: Status register */
#define ACQ_CORE_STA_FSM_ACQ_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Status register */
#define ACQ_CORE_STA_RESERVED1_MASK WBGEN2_GEN_MASK(4, 4)
#define ACQ_CORE_STA_RESERVED1_SHIFT 4
#define ACQ_CORE_STA_RESERVED1_W(value) WBGEN2_GEN_WRITE(value, 4, 4)
#define ACQ_CORE_STA_RESERVED1_R(reg) WBGEN2_GEN_READ(reg, 4, 4)
/* definitions for field: External flow control transfer status in reg: Status register */
#define ACQ_CORE_STA_FC_TRANS_DONE WBGEN2_GEN_MASK(8, 1)
/* definitions for field: External flow control FIFO full status in reg: Status register */
#define ACQ_CORE_STA_FC_FULL WBGEN2_GEN_MASK(9, 1)
/* definitions for field: Reserved in reg: Status register */
#define ACQ_CORE_STA_RESERVED2_MASK WBGEN2_GEN_MASK(10, 6)
#define ACQ_CORE_STA_RESERVED2_SHIFT 10
#define ACQ_CORE_STA_RESERVED2_W(value) WBGEN2_GEN_WRITE(value, 10, 6)
#define ACQ_CORE_STA_RESERVED2_R(reg) WBGEN2_GEN_READ(reg, 10, 6)
/* definitions for field: DDR3 transfer status in reg: Status register */
#define ACQ_CORE_STA_DDR3_TRANS_DONE WBGEN2_GEN_MASK(16, 1)
/* definitions for field: Reserved in reg: Status register */
#define ACQ_CORE_STA_RESERVED3_MASK WBGEN2_GEN_MASK(17, 15)
#define ACQ_CORE_STA_RESERVED3_SHIFT 17
#define ACQ_CORE_STA_RESERVED3_W(value) WBGEN2_GEN_WRITE(value, 17, 15)
#define ACQ_CORE_STA_RESERVED3_R(reg) WBGEN2_GEN_READ(reg, 17, 15)
/* definitions for register: Trigger configuration */
/* definitions for field: Hardware trigger selection in reg: Trigger configuration */
#define ACQ_CORE_TRIG_CFG_HW_TRIG_SEL WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Hardware trigger polarity in reg: Trigger configuration */
#define ACQ_CORE_TRIG_CFG_HW_TRIG_POL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Hardware trigger enable in reg: Trigger configuration */
#define ACQ_CORE_TRIG_CFG_HW_TRIG_EN WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Software trigger enable in reg: Trigger configuration */
#define ACQ_CORE_TRIG_CFG_SW_TRIG_EN WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Channel selection for internal trigger in reg: Trigger configuration */
#define ACQ_CORE_TRIG_CFG_INT_TRIG_SEL_MASK WBGEN2_GEN_MASK(4, 2)
#define ACQ_CORE_TRIG_CFG_INT_TRIG_SEL_SHIFT 4
#define ACQ_CORE_TRIG_CFG_INT_TRIG_SEL_W(value) WBGEN2_GEN_WRITE(value, 4, 2)
#define ACQ_CORE_TRIG_CFG_INT_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 4, 2)
/* definitions for field: Reserved in reg: Trigger configuration */
#define ACQ_CORE_TRIG_CFG_RESERVED_MASK WBGEN2_GEN_MASK(6, 10)
#define ACQ_CORE_TRIG_CFG_RESERVED_SHIFT 6
#define ACQ_CORE_TRIG_CFG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 6, 10)
#define ACQ_CORE_TRIG_CFG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 6, 10)
/* definitions for field: Threshold for internal trigger in reg: Trigger configuration */
#define ACQ_CORE_TRIG_CFG_INT_TRIG_THRES_MASK WBGEN2_GEN_MASK(16, 16)
#define ACQ_CORE_TRIG_CFG_INT_TRIG_THRES_SHIFT 16
#define ACQ_CORE_TRIG_CFG_INT_TRIG_THRES_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define ACQ_CORE_TRIG_CFG_INT_TRIG_THRES_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Trigger delay */
/* definitions for register: Software trigger */
/* definitions for register: Number of shots */
/* definitions for field: Number of shots in reg: Number of shots */
#define ACQ_CORE_SHOTS_NB_MASK WBGEN2_GEN_MASK(0, 16)
#define ACQ_CORE_SHOTS_NB_SHIFT 0
#define ACQ_CORE_SHOTS_NB_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define ACQ_CORE_SHOTS_NB_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Number of shots */
#define ACQ_CORE_SHOTS_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define ACQ_CORE_SHOTS_RESERVED_SHIFT 16
#define ACQ_CORE_SHOTS_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define ACQ_CORE_SHOTS_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Trigger address register */
/* definitions for register: Pre-trigger samples */
/* definitions for register: Post-trigger samples */
/* definitions for register: Samples counter */
/* definitions for register: DDR3 Start Address */
/* definitions for register: Acquisition channel control */
/* definitions for field: Acquisition channel selection in reg: Acquisition channel control */
#define ACQ_CORE_ACQ_CHAN_CTL_WHICH_MASK WBGEN2_GEN_MASK(0, 16)
#define ACQ_CORE_ACQ_CHAN_CTL_WHICH_SHIFT 0
#define ACQ_CORE_ACQ_CHAN_CTL_WHICH_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define ACQ_CORE_ACQ_CHAN_CTL_WHICH_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* [0x0]: REG Control register */
#define ACQ_CORE_REG_CTL 0x00000000
/* [0x4]: REG Status register */
#define ACQ_CORE_REG_STA 0x00000004
/* [0x8]: REG Trigger configuration */
#define ACQ_CORE_REG_TRIG_CFG 0x00000008
/* [0xc]: REG Trigger delay */
#define ACQ_CORE_REG_TRIG_DLY 0x0000000c
/* [0x10]: REG Software trigger */
#define ACQ_CORE_REG_SW_TRIG 0x00000010
/* [0x14]: REG Number of shots */
#define ACQ_CORE_REG_SHOTS 0x00000014
/* [0x18]: REG Trigger address register */
#define ACQ_CORE_REG_TRIG_POS 0x00000018
/* [0x1c]: REG Pre-trigger samples */
#define ACQ_CORE_REG_PRE_SAMPLES 0x0000001c
/* [0x20]: REG Post-trigger samples */
#define ACQ_CORE_REG_POST_SAMPLES 0x00000020
/* [0x24]: REG Samples counter */
#define ACQ_CORE_REG_SAMPLES_CNT 0x00000024
/* [0x28]: REG DDR3 Start Address */
#define ACQ_CORE_REG_DDR3_START_ADDR 0x00000028
/* [0x2c]: REG Acquisition channel control */
#define ACQ_CORE_REG_ACQ_CHAN_CTL 0x0000002c
#endif
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