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Beam Positoning Monitor - Gateware
Commit 957f0c0c authored by Adrian Byszuk's avatar Adrian Byszuk
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Fix TOP module for missing connections & testbench compatibility

parent 8208b2ee
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Showing with 14 additions and 8 deletions
hdl/top/pcie/bpm_pcie_k7.vhd
View file @ 957f0c0c
......@@ -34,7 +34,8 @@ use UNISIM.VComponents.all;
entity bpm_pcie_k7 is
generic (
constant pcieLanes : integer := C_NUM_PCIE_LANES
constant pcieLanes : integer := C_NUM_PCIE_LANES;
PL_FAST_TRAIN : string := "FALSE"
);
port (
......@@ -653,11 +654,11 @@ architecture Behavioral of bpm_pcie_k7 is
ctl_reset : out std_logic;
ctl_status : in std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: DLM Rx
dlm_rv : out std_logic;
dlm_rd : out std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
dlm_rv : in std_logic;
dlm_rd : in std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: DLM Tx
dlm_tv : in std_logic;
dlm_td : in std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
dlm_tv : out std_logic;
dlm_td : out std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
Link_Buf_full : in std_logic;
-- Data generator table write
tab_we : out std_logic_vector(2-1 downto 0);
......@@ -1250,8 +1251,8 @@ begin
tx_cfg_gnt <= '1';
s_axis_tx_tuser <= s_axis_tx_tdsc & '0' & s_axis_tx_terrfwd & '0';
m_axis_rx_tuser <= (others => '0');
m_axis_rx_tuser(1) <= m_axis_rx_terrfwd;
m_axis_rx_terrfwd <= m_axis_rx_tuser(1);
m_axis_rx_tbar_hit <= m_axis_rx_tuser(8 downto 2);
--
cfg_di <= (others => '0');
......@@ -1295,7 +1296,12 @@ begin
-- --------------------------------------------------------------
-- --------------------------------------------------------------
pcie_core_i : pcie_core port map(
pcie_core_i : pcie_core
generic map(
PL_FAST_TRAIN => PL_FAST_TRAIN,
PCIE_EXT_CLK => "FALSE"
)
port map(
--------------------------------------------------------------------------------------------------------------------
-- 1. PCI Express (pci_exp) Interface --
--------------------------------------------------------------------------------------------------------------------
......
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