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Commit 93a05e95 authored by Lucas Russo's avatar Lucas Russo
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hdl/*: various: no slave adapter for master ethmac interface (temp-fix)

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hdl/modules/ethmac/ethmac_pkg.vhd
View file @ 93a05e95
......@@ -49,7 +49,7 @@ package ethmac_pkg is
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_stall_o : out std_logic;
--wb_rty_o : out std_logic;
wb_rty_o : out std_logic;
-- WISHBONE master
m_wb_adr_o : out std_logic_vector(31 downto 0);
......@@ -62,7 +62,7 @@ package ethmac_pkg is
m_wb_ack_i : in std_logic;
m_wb_err_i : in std_logic;
m_wb_stall_i : in std_logic;
--m_wb_rty_i : in std_logic;
m_wb_rty_i : in std_logic;
-- PHY TX
mtx_clk_pad_i : in std_logic;
......
hdl/modules/ethmac/wb_ethmac.vhd
View file @ 93a05e95
......@@ -26,10 +26,10 @@ use work.ethmac_pkg.all;
entity wb_ethmac is
generic (
g_ma_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_ma_address_granularity : t_wishbone_address_granularity := WORD;
g_sl_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_sl_address_granularity : t_wishbone_address_granularity := WORD
g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_ma_address_granularity : t_wishbone_address_granularity := BYTE;
g_sl_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_sl_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
-- WISHBONE common
......@@ -48,6 +48,7 @@ port(
wb_err_o : out std_logic;
wb_stall_o : out std_logic;
--wb_rty_o : out std_logic;
wb_rty_o : out std_logic;
-- WISHBONE master
m_wb_adr_o : out std_logic_vector(31 downto 0);
......@@ -61,6 +62,7 @@ port(
m_wb_err_i : in std_logic;
m_wb_stall_i : in std_logic;
--m_wb_rty_i : in std_logic;
m_wb_rty_i : in std_logic;
-- PHY TX
mtx_clk_pad_i : in std_logic;
......@@ -186,43 +188,48 @@ begin
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o,
--sl_int_o => wb_int_o,
--sl_rty_o => wb_rty_o,
sl_rty_o => wb_rty_o,
sl_err_o => wb_err_o
);
--wb_rty_o <= '0';
-- Unused slave signals
wb_sl_out.rty <= '0';
wb_sl_out.stall <= '0';
wb_sl_out.int <= '0';
-- ETHMAC master interface is byte addressed, classic wishbone
cmp_ma_iface_slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => false,
g_master_mode => g_ma_interface_mode,
g_master_granularity => g_ma_address_granularity,
g_slave_use_struct => true,
g_slave_mode => CLASSIC,
g_slave_granularity => BYTE
)
port map (
clk_sys_i => wb_clk_i,
rst_n_i => rst_n,
slave_i => wb_ma_out,
slave_o => wb_ma_in,
ma_adr_o => m_wb_adr_o,
ma_dat_o => m_wb_dat_o,
ma_sel_o => m_wb_sel_o,
ma_cyc_o => m_wb_cyc_o,
ma_stb_o => m_wb_stb_o,
ma_we_o => m_wb_we_o,
ma_dat_i => m_wb_dat_i,
ma_ack_i => m_wb_ack_i,
ma_stall_i => m_wb_stall_i,
--ma_int_i => m_wb_int_i,
--ma_rty_i => m_wb_rty_i,
ma_err_i => m_wb_err_i
);
---- ETHMAC master interface is byte addressed, classic wishbone
-- NOT used for now
--cmp_ma_iface_slave_adapter : wb_slave_adapter
--generic map (
-- g_master_use_struct => false,
-- --g_master_mode => g_ma_interface_mode,
-- --g_master_granularity => g_ma_address_granularity,
-- g_master_mode => CLASSIC,
-- g_master_granularity => BYTE,
-- g_slave_use_struct => true,
-- g_slave_mode => CLASSIC,
-- g_slave_granularity => BYTE
--)
--port map (
-- clk_sys_i => wb_clk_i,
-- rst_n_i => rst_n,
-- slave_i => wb_ma_out,
-- slave_o => wb_ma_in,
-- ma_adr_o => m_wb_adr_o,
-- ma_dat_o => m_wb_dat_o,
-- ma_sel_o => m_wb_sel_o,
-- ma_cyc_o => m_wb_cyc_o,
-- ma_stb_o => m_wb_stb_o,
-- ma_we_o => m_wb_we_o,
-- ma_dat_i => m_wb_dat_i,
-- ma_ack_i => m_wb_ack_i,
-- ma_stall_i => m_wb_stall_i,
-- --ma_int_i => m_wb_int_i,
-- ma_rty_i => m_wb_rty_i,
-- ma_err_i => m_wb_err_i
--);
-- Unused slave signals
--wb_ma_in.rty <= '0';
......@@ -232,30 +239,50 @@ begin
cmp_wrapper_ethmac : ethmac
port map (
-- WISHBONE common
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
-- WISHBONE slave
wb_dat_i => wb_sl_in.dat,
wb_dat_o => wb_sl_out.dat,
wb_adr_i => wb_sl_in.adr(11 downto 2),
wb_sel_i => wb_sl_in.sel,
wb_we_i => wb_sl_in.we,
wb_cyc_i => wb_sl_in.cyc,
wb_stb_i => wb_sl_in.stb,
wb_ack_o => wb_sl_out.ack,
wb_err_o => wb_sl_out.err,
wb_sel_i => wb_sl_in.sel,
wb_we_i => wb_sl_in.we,
wb_cyc_i => wb_sl_in.cyc,
wb_stb_i => wb_sl_in.stb,
wb_ack_o => wb_sl_out.ack,
wb_err_o => wb_sl_out.err,
--wb_dat_i => wb_dat_i,
--wb_dat_o => wb_dat_o,
--wb_adr_i => wb_adr_i(11 downto 2),
--wb_sel_i => wb_sel_i,
--wb_we_i => wb_we_i,
--wb_cyc_i => wb_cyc_i,
--wb_stb_i => wb_stb_i,
--wb_ack_o => wb_ack_o,
--wb_err_o => wb_err_o,
-- WISHBONE master
m_wb_adr_o => wb_ma_out.adr,
m_wb_sel_o => wb_ma_out.sel,
m_wb_we_o => wb_ma_out.we,
m_wb_dat_o => wb_ma_out.dat,
m_wb_dat_i => wb_ma_in.dat,
m_wb_cyc_o => wb_ma_out.cyc,
m_wb_stb_o => wb_ma_out.stb,
m_wb_ack_i => wb_ma_in.ack,
m_wb_err_i => wb_ma_in.err,
--m_wb_adr_o => wb_ma_out.adr,
--m_wb_sel_o => wb_ma_out.sel,
--m_wb_we_o => wb_ma_out.we,
--m_wb_dat_o => wb_ma_out.dat,
--m_wb_dat_i => wb_ma_in.dat,
--m_wb_cyc_o => wb_ma_out.cyc,
--m_wb_stb_o => wb_ma_out.stb,
--m_wb_ack_i => wb_ma_in.ack,
--m_wb_err_i => wb_ma_in.err,
m_wb_adr_o => m_wb_adr_o,
m_wb_sel_o => m_wb_sel_o,
m_wb_we_o => m_wb_we_o,
m_wb_dat_o => m_wb_dat_o,
m_wb_dat_i => m_wb_dat_i,
m_wb_cyc_o => m_wb_cyc_o,
m_wb_stb_o => m_wb_stb_o,
m_wb_ack_i => m_wb_ack_i,
m_wb_err_i => m_wb_err_i,
-- PHY TX
mtx_clk_pad_i => mtx_clk_pad_i,
......@@ -264,11 +291,11 @@ begin
mtxerr_pad_o => mtxerr_pad_o,
-- PHY RX
mrx_clk_pad_i => mrx_clk_pad_i,
mrx_clk_pad_i => mrx_clk_pad_i,
mrxd_pad_i => mrxd_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxerr_pad_i => mrxerr_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcrs_pad_i => mcrs_pad_i,
-- MII
......@@ -278,6 +305,6 @@ begin
md_padoe_o => md_padoe_o,
-- Interrupt
int_o => int_o
int_o => int_o
);
end rtl;
hdl/modules/ethmac/xwb_ethmac.vhd
View file @ 93a05e95
......@@ -71,8 +71,37 @@ end xwb_ethmac;
architecture rtl of xwb_ethmac is
--signal mac_m_idle : std_logic;
--signal wb_slave_out_ack_int : std_logic;
--signal wb_master_out_stb_int : std_logic;
--signal wb_master_out_cyc_int : std_logic;
begin
-- Wishbone B4 master to B2 slave
--wb_slave_out.STALL <= wb_slave_in.CYC AND (NOT wb_slave_out_ack_int);
--wb_slave_out.ACK <= wb_slave_out_ack_int;
--wb_slave_out.RTY <= '0';
--
---- Wishbone B2 master to B4 slave
--wb_master_out.STB <= wb_master_out_stb_int when mac_m_idle='1' else '0';
--wb_master_out.CYC <= wb_master_out_cyc_int;
--
--macStateMachine : process(wb_clk_i)
--begin
-- if (rising_edge(wb_clk_i)) then
-- if wb_rst_i = '1' then
-- mac_m_idle <= '1';
-- else
-- if (wb_master_in.ACK = '1' and wb_master_out_cyc_int = '1') then
-- mac_m_idle <= '1';
-- elsif (wb_master_out_stb_int = '1' and wb_master_out_cyc_int = '1') then
-- mac_m_idle <= '0';
-- end if;
-- end if;
-- end if;
--end process;
cmp_wrapper_wb_ethmac : wb_ethmac
generic map (
g_ma_interface_mode => g_ma_interface_mode,
......@@ -82,34 +111,39 @@ begin
)
port map(
-- WISHBONE common
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
-- WISHBONE slave
wb_dat_i => wb_slave_in.dat,
wb_dat_o => wb_slave_out.dat,
wb_adr_i => wb_slave_in.adr(11 downto 0),
wb_sel_i => wb_slave_in.sel,
wb_we_i => wb_slave_in.we,
wb_cyc_i => wb_slave_in.cyc,
wb_stb_i => wb_slave_in.stb,
wb_ack_o => wb_slave_out.ack,
wb_err_o => wb_slave_out.err,
wb_sel_i => wb_slave_in.sel,
wb_we_i => wb_slave_in.we,
wb_cyc_i => wb_slave_in.cyc,
wb_stb_i => wb_slave_in.stb,
wb_ack_o => wb_slave_out.ack,
--wb_ack_o => wb_slave_out_ack_int,
wb_err_o => wb_slave_out.err,
wb_stall_o => wb_slave_out.stall,
wb_rty_o => wb_slave_out.rty,
--wb_rty_o => wb_slave_out.rty,
-- WISHBONE master
m_wb_adr_o => wb_master_out.adr,
m_wb_sel_o => wb_master_out.sel,
m_wb_we_o => wb_master_out.we,
m_wb_we_o => wb_master_out.we,
m_wb_dat_o => wb_master_out.dat,
m_wb_dat_i => wb_master_in.dat,
m_wb_cyc_o => wb_master_out.cyc,
m_wb_stb_o => wb_master_out.stb,
--m_wb_cyc_o => wb_master_out_cyc_int,
--m_wb_stb_o => wb_master_out_stb_int,
m_wb_ack_i => wb_master_in.ack,
m_wb_err_i => wb_master_in.err,
m_wb_stall_i => wb_master_in.stall,
--m_wb_rty_i => wb_master_in.rty,
m_wb_rty_i => wb_master_in.rty,
-- PHY TX
mtx_clk_pad_i => mtx_clk_pad_i,
......@@ -118,11 +152,11 @@ begin
mtxerr_pad_o => mtxerr_pad_o,
-- PHY RX
mrx_clk_pad_i => mrx_clk_pad_i,
mrx_clk_pad_i => mrx_clk_pad_i,
mrxd_pad_i => mrxd_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxerr_pad_i => mrxerr_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcrs_pad_i => mcrs_pad_i,
-- MII
......@@ -132,6 +166,6 @@ begin
md_padoe_o => md_padoe_o,
-- Interrupt
int_o => int_o
int_o => int_o
);
end rtl;
hdl/syn/dbe_bpm_ebone/make_output
View file @ 93a05e95
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/top/ml_605/dbe_bpm_ebone/chipscope.cpj 0 → 100644
View file @ 93a05e95
#ChipScope Pro Analyzer Project File, Version 3.0
#Mon Feb 18 08:45:03 BRT 2013
mdiAreaHeight=0.6997716894977168
mdiAreaHeightLast=0.6997716894977168
mdiCount=0
navigatorHeight=0.17922374429223745
navigatorHeightLast=0.17922374429223745
navigatorWidth=0.17963576158940397
navigatorWidthLast=0.17963576158940397
signalDisplayPath=0
unit.-1.-1.username=
#Allows chipscope to avoid scanning certain USER registers.
#This allows the use of chipscope with other BSCAN primitives
#in the same design. See: http://www.xilinx.com/support/answers
#/31596.htm
#Avoids scanning the USER registers 1, 2 and 3 for the second device
#(FPGA) in the chain. Device 0 is the SystemACE
avoidUserRegDevice0=1,2,3
hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd
View file @ 93a05e95
......@@ -504,7 +504,7 @@ begin
g_size => c_dpram_ethbuf_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => PIPELINED,
g_slave1_interface_mode => CLASSIC,
--g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
--g_slave2_granularity => BYTE
......@@ -523,10 +523,10 @@ begin
-- The Ethernet MAC is master 4, slave 4
cmp_xwb_ethmac : xwb_ethmac
generic map (
g_ma_interface_mode => PIPELINED,
--g_ma_interface_mode => CLASSIC,
--g_ma_interface_mode => PIPELINED,
g_ma_interface_mode => CLASSIC, -- NOT used for now
--g_ma_address_granularity => WORD,
g_ma_address_granularity => BYTE,
g_ma_address_granularity => BYTE, -- NOT used for now
g_sl_interface_mode => PIPELINED,
--g_sl_interface_mode => CLASSIC,
--g_sl_address_granularity => WORD
......
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