Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
B
Beam Positoning Monitor - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Beam Positoning Monitor - Gateware
Commits
8f88e350
Commit
8f88e350
authored
May 10, 2016
by
Vitor Finotti
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Removed xwb_trigger declaration (it is in dbe_wishbone_pkg)
parent
cfcc18e2
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
1 addition
and
26 deletions
+1
-26
wb_trigger_top.vhd
hdl/top/afc_v3/vivado/wb_trigger/wb_trigger_top.vhd
+1
-26
No files found.
hdl/top/afc_v3/vivado/wb_trigger/wb_trigger_top.vhd
View file @
8f88e350
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Vitor Finotti Ferreira <vfinotti@finotti-Inspiron-7520>
-- Author : Vitor Finotti Ferreira <vfinotti@finotti-Inspiron-7520>
-- Company : Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- Company : Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- Created : 2016-02-02
-- Created : 2016-02-02
-- Last update: 2016-0
2-04
-- Last update: 2016-0
5-10
-- Platform :
-- Platform :
-- Standard : VHDL'93/02
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -117,31 +117,6 @@ end wb_trigger_top;
...
@@ -117,31 +117,6 @@ end wb_trigger_top;
architecture
structural
of
wb_trigger_top
is
architecture
structural
of
wb_trigger_top
is
-------------------------------------------------------------------------------
-- Core
-------------------------------------------------------------------------------
component
xwb_trigger
is
generic
(
g_width_bus_size
:
positive
;
g_rcv_len_bus_width
:
positive
;
g_transm_len_bus_width
:
positive
;
g_sync_edge
:
string
;
g_trig_num
:
positive
;
g_counter_wid
:
positive
);
port
(
rst_n_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
fs_clk_i
:
in
std_logic
;
fs_rst_n_i
:
in
std_logic
;
wb_slv_i
:
in
t_wishbone_slave_in
;
wb_slv_o
:
out
t_wishbone_slave_out
;
trig_dir_o
:
out
std_logic_vector
(
g_trig_num
-1
downto
0
);
trig_pulse_transm_i
:
in
std_logic_vector
(
g_trig_num
-1
downto
0
);
trig_pulse_rcv_o
:
out
std_logic_vector
(
g_trig_num
-1
downto
0
);
trig_b
:
inout
std_logic_vector
(
g_trig_num
-1
downto
0
));
end
component
xwb_trigger
;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Chipscope
-- Chipscope
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment