various: rename wishbone and common folders

Now, custom_wishbone is dbe_wishbone and custom_common is dbe_common

various: rename wishbone and common folders
Now, custom_wishbone is dbe_wishbone and custom_common is dbe_common
8960ece8 · Lucas Russo · d89ef5f1 · 8960ece8 · 8960ece8 · 8960ece8
Commit 8960ece8 authored Aug 19, 2013 by Lucas Russo
175 changed files
--- a/hdl/Manifest.py
+++ b/hdl/Manifest.py
 #fetchto = "ip_cores"

 modules = { "local": [
-                "modules/custom_wishbone",
-                "modules/custom_common",
+                "modules/dbe_wishbone",
+                "modules/dbe_common",
                "modules/rffe_top",
-                "modules/ethmac",
                "modules/fabric",
                "ip_cores/general-cores",
                "ip_cores/etherbone-core",

--- a/hdl/modules/custom_common/Manifest.py
+++ b/hdl/modules/custom_common/Manifest.py
 modules = { "local" : ["reset_synch"] };

-files = [ "custom_common_pkg.vhd" ];
+files = [ "dbe_common_pkg.vhd" ];
--- a/hdl/modules/custom_common/custom_common_pkg.vhd
+++ b/hdl/modules/custom_common/custom_common_pkg.vhd
 library ieee;
 use ieee.std_logic_1164.all;

-package custom_common_pkg is
+package dbe_common_pkg is

    --------------------------------------------------------------------
    -- Components
    --------------------------------------------------------------------
-    
+
    component reset_synch
-    port 
+    port
    (
        clk_i                     : in  std_logic;
        arst_n_i                : in  std_logic;
        rst_n_o                  : out std_logic
    );
    end component;
-    
-end custom_common_pkg;
+
+end dbe_common_pkg;
--- a/hdl/modules/custom_common/reset_synch/Manifest.py
+++ b/hdl/modules/custom_common/reset_synch/Manifest.py
--- a/hdl/modules/custom_common/reset_synch/reset_synch.vhd
+++ b/hdl/modules/custom_common/reset_synch/reset_synch.vhd
--- a/hdl/modules/custom_wishbone/Manifest.py
+++ b/hdl/modules/custom_wishbone/Manifest.py
-files = [ "custom_wishbone_pkg.vhd" ];
+files = [ "dbe_wishbone_pkg.vhd" ];

 modules = { "local" : [
                        "wb_stream",
                        "wb_fmc150",
                        "wb_fmc516",
-			"wb_ethmac_adapter",
-			"wb_dbe_periph",
-#			"wb_fmc_iface"
+                        "wb_ethmac_adapter",
+                        "wb_ethmac",
+                        "wb_dbe_periph"
                      ] };
--- a/hdl/modules/custom_wishbone/custom_wishbone_pkg.vhd
+++ b/hdl/modules/custom_wishbone/custom_wishbone_pkg.vhd
@@ -8,7 +8,7 @@ use work.wb_stream_generic_pkg.all;
 use work.fmc516_pkg.all;
 use work.wr_fabric_pkg.all;

-package custom_wishbone_pkg is
+package dbe_wishbone_pkg is

  --------------------------------------------------------------------
  -- Components
@@ -923,4 +923,4 @@ package custom_wishbone_pkg is
    date          => x"20130703",
    name          => "LNLS_POSITION_CALC ")));

-end custom_wishbone_pkg;
+end dbe_wishbone_pkg;
--- a/hdl/modules/custom_wishbone/wb_dbe_periph/Manifest.py
+++ b/hdl/modules/custom_wishbone/wb_dbe_periph/Manifest.py
--- a/hdl/modules/custom_wishbone/wb_dbe_periph/wb_dbe_periph.vhd
+++ b/hdl/modules/custom_wishbone/wb_dbe_periph/wb_dbe_periph.vhd
@@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

 library work;
-use work.custom_wishbone_pkg.all;
+use work.dbe_wishbone_pkg.all;
 use work.wishbone_pkg.all;

 entity wb_dbe_periph is

--- a/hdl/modules/custom_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd
+++ b/hdl/modules/custom_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd
@@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

 library work;
-use work.custom_wishbone_pkg.all;
+use work.dbe_wishbone_pkg.all;
 use work.wishbone_pkg.all;

 entity xwb_dbe_periph is

--- a/hdl/modules/custom_wishbone/wb_dma_interface_FIX/Manifest.py
+++ b/hdl/modules/custom_wishbone/wb_dma_interface_FIX/Manifest.py
--- a/hdl/modules/custom_wishbone/wb_dma_interface_FIX/dma_status_reg_synch.vhd
+++ b/hdl/modules/custom_wishbone/wb_dma_interface_FIX/dma_status_reg_synch.vhd
--- a/hdl/modules/custom_wishbone/wb_dma_interface_FIX/doc/wb_dma_ctl_iface.html
+++ b/hdl/modules/custom_wishbone/wb_dma_interface_FIX/doc/wb_dma_ctl_iface.html
--- a/hdl/modules/custom_wishbone/wb_dma_interface_FIX/doc/wb_xdma_interface.html
+++ b/hdl/modules/custom_wishbone/wb_dma_interface_FIX/doc/wb_xdma_interface.html
--- a/hdl/modules/custom_wishbone/wb_dma_interface_FIX/old/xdma_interface_registers_pkg.vhd
+++ b/hdl/modules/custom_wishbone/wb_dma_interface_FIX/old/xdma_interface_registers_pkg.vhd
--- a/hdl/modules/custom_wishbone/wb_dma_interface_FIX/old/xdma_interface_regs.h
+++ b/hdl/modules/custom_wishbone/wb_dma_interface_FIX/old/xdma_interface_regs.h
--- a/hdl/modules/custom_wishbone/wb_dma_interface_FIX/old/xdma_interface_wb.vhd
+++ b/hdl/modules/custom_wishbone/wb_dma_interface_FIX/old/xdma_interface_wb.vhd
--- a/hdl/modules/custom_wishbone/wb_dma_interface_FIX/old/xdma_interface_wb.wb
+++ b/hdl/modules/custom_wishbone/wb_dma_interface_FIX/old/xdma_interface_wb.wb
--- a/hdl/modules/custom_wishbone/wb_dma_interface_FIX/wb_dma_interface.old.vhd
+++ b/hdl/modules/custom_wishbone/wb_dma_interface_FIX/wb_dma_interface.old.vhd
@@ -10,7 +10,7 @@ library work;
 use work.genram_pkg.all;
 use work.gencores_pkg.all;
 use work.wishbone_pkg.all;
-use work.custom_wishbone_pkg.all;
+use work.dbe_wishbone_pkg.all;
 use work.custom_common_pkg.all;

 ------------------------------------------------------------------------------

--- a/hdl/modules/custom_wishbone/wb_dma_interface_FIX/wb_dma_interface.vhd
+++ b/hdl/modules/custom_wishbone/wb_dma_interface_FIX/wb_dma_interface.vhd
@@ -10,7 +10,7 @@ library work;
 use work.genram_pkg.all;
 use work.gencores_pkg.all;
 use work.wishbone_pkg.all;
-use work.custom_wishbone_pkg.all;
+use work.dbe_wishbone_pkg.all;
 use work.custom_common_pkg.all;

 ------------------------------------------------------------------------------

--- a/hdl/modules/custom_wishbone/wb_dma_interface_FIX/xdma_interface.wb
+++ b/hdl/modules/custom_wishbone/wb_dma_interface_FIX/xdma_interface.wb
--- a/hdl/modules/custom_wishbone/wb_dma_interface_FIX/xwb_dma_interface.old.vhd
+++ b/hdl/modules/custom_wishbone/wb_dma_interface_FIX/xwb_dma_interface.old.vhd
@@ -8,7 +8,7 @@ use ieee.numeric_std.all;

 library work;
 use work.wishbone_pkg.all;
-use work.custom_wishbone_pkg.all;
+use work.dbe_wishbone_pkg.all;

 ------------------------------------------------------------------------------
 -- Entity section

--- a/hdl/modules/custom_wishbone/wb_dma_interface_FIX/xwb_dma_interface.vhd
+++ b/hdl/modules/custom_wishbone/wb_dma_interface_FIX/xwb_dma_interface.vhd
@@ -8,7 +8,7 @@ use ieee.numeric_std.all;

 library work;
 use work.wishbone_pkg.all;
-use work.custom_wishbone_pkg.all;
+use work.dbe_wishbone_pkg.all;

 ------------------------------------------------------------------------------
 -- Entity section

--- a/hdl/modules/ethmac/BUGS
+++ b/hdl/modules/ethmac/BUGS
--- a/hdl/modules/ethmac/Manifest.py
+++ b/hdl/modules/ethmac/Manifest.py
--- a/hdl/modules/ethmac/README
+++ b/hdl/modules/ethmac/README
--- a/hdl/modules/ethmac/TODO
+++ b/hdl/modules/ethmac/TODO
--- a/hdl/modules/ethmac/eth_clockgen.v
+++ b/hdl/modules/ethmac/eth_clockgen.v
--- a/hdl/modules/ethmac/eth_cop.v
+++ b/hdl/modules/ethmac/eth_cop.v
--- a/hdl/modules/ethmac/eth_crc.v
+++ b/hdl/modules/ethmac/eth_crc.v
--- a/hdl/modules/ethmac/eth_defines.v
+++ b/hdl/modules/ethmac/eth_defines.v
--- a/hdl/modules/ethmac/eth_fifo.v
+++ b/hdl/modules/ethmac/eth_fifo.v
--- a/hdl/modules/ethmac/eth_maccontrol.v
+++ b/hdl/modules/ethmac/eth_maccontrol.v
--- a/hdl/modules/ethmac/eth_macstatus.v
+++ b/hdl/modules/ethmac/eth_macstatus.v
--- a/hdl/modules/ethmac/eth_miim.v
+++ b/hdl/modules/ethmac/eth_miim.v
--- a/hdl/modules/ethmac/eth_outputcontrol.v
+++ b/hdl/modules/ethmac/eth_outputcontrol.v
--- a/hdl/modules/ethmac/eth_random.v
+++ b/hdl/modules/ethmac/eth_random.v
--- a/hdl/modules/ethmac/eth_receivecontrol.v
+++ b/hdl/modules/ethmac/eth_receivecontrol.v
--- a/hdl/modules/ethmac/eth_register.v
+++ b/hdl/modules/ethmac/eth_register.v
--- a/hdl/modules/ethmac/eth_registers.v
+++ b/hdl/modules/ethmac/eth_registers.v
--- a/hdl/modules/ethmac/eth_rxaddrcheck.v
+++ b/hdl/modules/ethmac/eth_rxaddrcheck.v
--- a/hdl/modules/ethmac/eth_rxcounters.v
+++ b/hdl/modules/ethmac/eth_rxcounters.v
--- a/hdl/modules/ethmac/eth_rxethmac.v
+++ b/hdl/modules/ethmac/eth_rxethmac.v
--- a/hdl/modules/ethmac/eth_rxstatem.v
+++ b/hdl/modules/ethmac/eth_rxstatem.v
--- a/hdl/modules/ethmac/eth_shiftreg.v
+++ b/hdl/modules/ethmac/eth_shiftreg.v
--- a/hdl/modules/ethmac/eth_spram_256x32.v
+++ b/hdl/modules/ethmac/eth_spram_256x32.v
--- a/hdl/modules/ethmac/eth_top.v
+++ b/hdl/modules/ethmac/eth_top.v
--- a/hdl/modules/ethmac/eth_transmitcontrol.v
+++ b/hdl/modules/ethmac/eth_transmitcontrol.v
--- a/hdl/modules/ethmac/eth_txcounters.v
+++ b/hdl/modules/ethmac/eth_txcounters.v
--- a/hdl/modules/ethmac/eth_txethmac.v
+++ b/hdl/modules/ethmac/eth_txethmac.v
--- a/hdl/modules/ethmac/eth_txstatem.v
+++ b/hdl/modules/ethmac/eth_txstatem.v
--- a/hdl/modules/ethmac/eth_wishbone.v
+++ b/hdl/modules/ethmac/eth_wishbone.v
--- a/hdl/modules/ethmac/ethmac.v
+++ b/hdl/modules/ethmac/ethmac.v
--- a/hdl/modules/ethmac/ethmac_defines.v
+++ b/hdl/modules/ethmac/ethmac_defines.v
--- a/hdl/modules/ethmac/ethmac_pkg.vhd
+++ b/hdl/modules/ethmac/ethmac_pkg.vhd
--- a/hdl/modules/ethmac/timescale.v
+++ b/hdl/modules/ethmac/timescale.v
--- a/hdl/modules/ethmac/wb_ethmac.vhd
+++ b/hdl/modules/ethmac/wb_ethmac.vhd
--- a/hdl/modules/ethmac/xilinx_dist_ram_16x32.v
+++ b/hdl/modules/ethmac/xilinx_dist_ram_16x32.v
--- a/hdl/modules/ethmac/xwb_ethmac.vhd
+++ b/hdl/modules/ethmac/xwb_ethmac.vhd
--- a/hdl/modules/custom_wishbone/wb_ethmac_adapter/Manifest.py
+++ b/hdl/modules/custom_wishbone/wb_ethmac_adapter/Manifest.py
--- a/hdl/modules/custom_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd
+++ b/hdl/modules/custom_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/Manifest.py
+++ b/hdl/modules/custom_wishbone/wb_fmc150/Manifest.py
--- a/hdl/modules/custom_wishbone/wb_fmc150/adc/Manifest.py
+++ b/hdl/modules/custom_wishbone/wb_fmc150/adc/Manifest.py
--- a/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_pkg.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_pkg.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/adc/strobe_lvds.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/adc/strobe_lvds.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/build_wb.sh
+++ b/hdl/modules/custom_wishbone/wb_fmc150/build_wb.sh
--- a/hdl/modules/custom_wishbone/wb_fmc150/doc/xfmc150_regs_wb.html
+++ b/hdl/modules/custom_wishbone/wb_fmc150/doc/xfmc150_regs_wb.html
--- a/hdl/modules/custom_wishbone/wb_fmc150/fmc150/Manifest.py
+++ b/hdl/modules/custom_wishbone/wb_fmc150/fmc150/Manifest.py
--- a/hdl/modules/custom_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/Manifest.py
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/Manifest.py
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/ads62p49_init_mem.ngc
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/ads62p49_init_mem.ngc
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/amc7823_init_mem.ngc
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/amc7823_init_mem.ngc
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/cdce72010_init_mem_ext.ngc
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/cdce72010_init_mem_ext.ngc
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/cdce72010_init_mem_int.ngc
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/cdce72010_init_mem_int.ngc
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/ads62p49_init.coe
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/ads62p49_init.coe
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/amc7823_init.coe
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/amc7823_init.coe
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/cdce72010_init_ext_491_52MHz.coe
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/cdce72010_init_ext_491_52MHz.coe
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/cdce72010_init_ext_737_28MHz.coe
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/cdce72010_init_ext_737_28MHz.coe
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/cdce72010_init_ext_7_68MHz.coe
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/cdce72010_init_ext_7_68MHz.coe
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/cdce72010_init_int_491_52MHz.coe
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/cdce72010_init_int_491_52MHz.coe
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/cdce72010_init_int_737_28MHz.coe
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/cdce72010_init_int_737_28MHz.coe
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/dac3283_init.coe
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/coe/dac3283_init.coe
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/dac3283_init_mem.ngc
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/dac3283_init_mem.ngc
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/old_netlist/ads62p49_init_mem.ngc
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/old_netlist/ads62p49_init_mem.ngc
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/old_netlist/amc7823_init_mem.ngc
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/old_netlist/amc7823_init_mem.ngc
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/old_netlist/cdce72010_init_mem_ext.ngc
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/old_netlist/cdce72010_init_mem_ext.ngc
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/old_netlist/cdce72010_init_mem_int.ngc
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/old_netlist/cdce72010_init_mem_int.ngc
--- a/hdl/modules/custom_wishbone/wb_fmc150/netlist/old_netlist/dac3283_init_mem.ngc
+++ b/hdl/modules/custom_wishbone/wb_fmc150/netlist/old_netlist/dac3283_init_mem.ngc
--- a/hdl/modules/custom_wishbone/wb_fmc150/sim/Manifest.py
+++ b/hdl/modules/custom_wishbone/wb_fmc150/sim/Manifest.py
--- a/hdl/modules/custom_wishbone/wb_fmc150/sim/ads62p49_init_mem.mif
+++ b/hdl/modules/custom_wishbone/wb_fmc150/sim/ads62p49_init_mem.mif
--- a/hdl/modules/custom_wishbone/wb_fmc150/sim/ads62p49_init_mem.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/sim/ads62p49_init_mem.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/sim/amc7823_init_mem.mif
+++ b/hdl/modules/custom_wishbone/wb_fmc150/sim/amc7823_init_mem.mif
--- a/hdl/modules/custom_wishbone/wb_fmc150/sim/amc7823_init_mem.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/sim/amc7823_init_mem.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/sim/cdce72010_init_mem_ext.mif
+++ b/hdl/modules/custom_wishbone/wb_fmc150/sim/cdce72010_init_mem_ext.mif
--- a/hdl/modules/custom_wishbone/wb_fmc150/sim/cdce72010_init_mem_ext.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/sim/cdce72010_init_mem_ext.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/sim/cdce72010_init_mem_int.mif
+++ b/hdl/modules/custom_wishbone/wb_fmc150/sim/cdce72010_init_mem_int.mif
--- a/hdl/modules/custom_wishbone/wb_fmc150/sim/cdce72010_init_mem_int.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/sim/cdce72010_init_mem_int.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/sim/dac3283_init_mem.mif
+++ b/hdl/modules/custom_wishbone/wb_fmc150/sim/dac3283_init_mem.mif
--- a/hdl/modules/custom_wishbone/wb_fmc150/sim/dac3283_init_mem.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/sim/dac3283_init_mem.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.h
+++ b/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.h
--- a/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150_port.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150_port.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/xfmc150.wb
+++ b/hdl/modules/custom_wishbone/wb_fmc150/xfmc150.wb
--- a/hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc516/Manifest.py
+++ b/hdl/modules/custom_wishbone/wb_fmc516/Manifest.py
--- a/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_buf.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_buf.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_clk.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_clk.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_iface.old.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_iface.old.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_iface.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_iface.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_sync_chains.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_sync_chains.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc516/fmc516_ml605.ucf
+++ b/hdl/modules/custom_wishbone/wb_fmc516/fmc516_ml605.ucf
--- a/hdl/modules/custom_wishbone/wb_fmc516/fmc516_pkg.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc516/fmc516_pkg.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc516/wbgen/build_wb.sh
+++ b/hdl/modules/custom_wishbone/wb_fmc516/wbgen/build_wb.sh
--- a/hdl/modules/custom_wishbone/wb_fmc516/wbgen/doc/fmc516_regs_wb.html
+++ b/hdl/modules/custom_wishbone/wb_fmc516/wbgen/doc/fmc516_regs_wb.html
--- a/hdl/modules/custom_wishbone/wb_fmc516/wbgen/fmc516_regs.h
+++ b/hdl/modules/custom_wishbone/wb_fmc516/wbgen/fmc516_regs.h
--- a/hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.wb
+++ b/hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.wb
--- a/hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs_pkg.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs_pkg.vhd
--- a/hdl/modules/custom_wishbone/wb_fmc516/xwb_fmc516.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc516/xwb_fmc516.vhd
--- a/hdl/modules/custom_wishbone/wb_irq_mngr/Manifest.py
+++ b/hdl/modules/custom_wishbone/wb_irq_mngr/Manifest.py
--- a/hdl/modules/custom_wishbone/wb_irq_mngr/wb_irq_mngr.vhd
+++ b/hdl/modules/custom_wishbone/wb_irq_mngr/wb_irq_mngr.vhd
--- a/hdl/modules/custom_wishbone/wb_irq_mngr/xwb_irq_mngr.vhd
+++ b/hdl/modules/custom_wishbone/wb_irq_mngr/xwb_irq_mngr.vhd
--- a/hdl/modules/custom_wishbone/wb_stream/Manifest.py
+++ b/hdl/modules/custom_wishbone/wb_stream/Manifest.py
--- a/hdl/modules/custom_wishbone/wb_stream/generic/Manifest.py
+++ b/hdl/modules/custom_wishbone/wb_stream/generic/Manifest.py
--- a/hdl/modules/custom_wishbone/wb_stream/generic/wb_stream_generic_pkg.vhd
+++ b/hdl/modules/custom_wishbone/wb_stream/generic/wb_stream_generic_pkg.vhd
--- a/hdl/modules/custom_wishbone/wb_stream/generic/wb_stream_generic_vhdl_2008_pkg.vhd
+++ b/hdl/modules/custom_wishbone/wb_stream/generic/wb_stream_generic_vhdl_2008_pkg.vhd
--- a/hdl/modules/custom_wishbone/wb_stream/generic/wb_stream_sink_gen.vhd
+++ b/hdl/modules/custom_wishbone/wb_stream/generic/wb_stream_sink_gen.vhd
--- a/hdl/modules/custom_wishbone/wb_stream/generic/wb_stream_source_gen.vhd
+++ b/hdl/modules/custom_wishbone/wb_stream/generic/wb_stream_source_gen.vhd
--- a/hdl/modules/custom_wishbone/wb_stream/generic/xwb_stream_sink_gen.vhd
+++ b/hdl/modules/custom_wishbone/wb_stream/generic/xwb_stream_sink_gen.vhd
--- a/hdl/modules/custom_wishbone/wb_stream/generic/xwb_stream_source_gen.vhd
+++ b/hdl/modules/custom_wishbone/wb_stream/generic/xwb_stream_source_gen.vhd
--- a/hdl/modules/custom_wishbone/wb_stream/wb_stream_pkg.vhd
+++ b/hdl/modules/custom_wishbone/wb_stream/wb_stream_pkg.vhd
--- a/hdl/modules/custom_wishbone/wb_stream/xwb_stream_sink.vhd
+++ b/hdl/modules/custom_wishbone/wb_stream/xwb_stream_sink.vhd
--- a/hdl/modules/custom_wishbone/wb_stream/xwb_stream_source.vhd
+++ b/hdl/modules/custom_wishbone/wb_stream/xwb_stream_source.vhd
--- a/hdl/syn/dbe_bpm_ebone/dbe_bpm_ebone.xise
+++ b/hdl/syn/dbe_bpm_ebone/dbe_bpm_ebone.xise
--- a/hdl/syn/dbe_bpm_ebone/make_output
+++ b/hdl/syn/dbe_bpm_ebone/make_output
--- a/hdl/syn/dbe_bpm_fmc516/Manifest.py
+++ b/hdl/syn/dbe_bpm_fmc516/Manifest.py
--- a/hdl/syn/dbe_bpm_fmc516/dbe_bpm_fmc516.xise
+++ b/hdl/syn/dbe_bpm_fmc516/dbe_bpm_fmc516.xise
--- a/hdl/syn/dbe_bpm_fmc516/make_output
+++ b/hdl/syn/dbe_bpm_fmc516/make_output
--- a/hdl/syn/dbe_bpm_simple/dbe_bpm_simple.xise
+++ b/hdl/syn/dbe_bpm_simple/dbe_bpm_simple.xise
--- a/hdl/syn/dbe_bpm_simple/make_output
+++ b/hdl/syn/dbe_bpm_simple/make_output
--- a/hdl/testbench/wishbone/system_test/Makefile
+++ b/hdl/testbench/wishbone/system_test/Makefile
--- a/hdl/testbench/wishbone/system_test/dbe_bpm_simple_top.vhd
+++ b/hdl/testbench/wishbone/system_test/dbe_bpm_simple_top.vhd
--- a/hdl/testbench/wishbone/system_test/system_test_tb.vhd
+++ b/hdl/testbench/wishbone/system_test/system_test_tb.vhd
--- a/hdl/testbench/wishbone/wb_dma_interface_test/Makefile
+++ b/hdl/testbench/wishbone/wb_dma_interface_test/Makefile
--- a/hdl/testbench/wishbone/wb_dma_interface_test/wb_dma_interface_tb.vhd
+++ b/hdl/testbench/wishbone/wb_dma_interface_test/wb_dma_interface_tb.vhd
--- a/hdl/testbench/wishbone/wb_ethmac_adapter_test/vhdl/Makefile
+++ b/hdl/testbench/wishbone/wb_ethmac_adapter_test/vhdl/Makefile
--- a/hdl/testbench/wishbone/wb_ethmac_adapter_test/vhdl/wave.wcfg
+++ b/hdl/testbench/wishbone/wb_ethmac_adapter_test/vhdl/wave.wcfg
--- a/hdl/testbench/wishbone/wb_ethmac_adapter_test/vhdl/xwb_ethmac_adapter_tb.vhd
+++ b/hdl/testbench/wishbone/wb_ethmac_adapter_test/vhdl/xwb_ethmac_adapter_tb.vhd
--- a/hdl/testbench/wishbone/wb_fmc150_test/verilog/Makefile
+++ b/hdl/testbench/wishbone/wb_fmc150_test/verilog/Makefile
--- a/hdl/testbench/wishbone/wb_fmc150_test/verilog/wave.wcfg
+++ b/hdl/testbench/wishbone/wb_fmc150_test/verilog/wave.wcfg
--- a/hdl/testbench/wishbone/wb_fmc150_test/vhdl/Makefile
+++ b/hdl/testbench/wishbone/wb_fmc150_test/vhdl/Makefile
--- a/hdl/testbench/wishbone/wb_fmc150_test/vhdl/wave.wcfg
+++ b/hdl/testbench/wishbone/wb_fmc150_test/vhdl/wave.wcfg
--- a/hdl/testbench/wishbone/wb_fmc150_test/vhdl/wb_fmc150_tb.vhd
+++ b/hdl/testbench/wishbone/wb_fmc150_test/vhdl/wb_fmc150_tb.vhd
--- a/hdl/testbench/wishbone/wb_fmc516_test/verilog/Makefile
+++ b/hdl/testbench/wishbone/wb_fmc516_test/verilog/Makefile
--- a/hdl/testbench/wishbone/wb_fmc516_test/verilog/wave.wcfg
+++ b/hdl/testbench/wishbone/wb_fmc516_test/verilog/wave.wcfg
--- a/hdl/testbench/wishbone/wb_fmc516_test/vhdl/Makefile
+++ b/hdl/testbench/wishbone/wb_fmc516_test/vhdl/Makefile
--- a/hdl/testbench/wishbone/wb_fmc516_test/vhdl/wave.wcfg
+++ b/hdl/testbench/wishbone/wb_fmc516_test/vhdl/wave.wcfg
--- a/hdl/testbench/wishbone/wb_fmc516_test/vhdl/wb_fmc516_tb.vhd
+++ b/hdl/testbench/wishbone/wb_fmc516_test/vhdl/wb_fmc516_tb.vhd
--- a/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd
+++ b/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd
--- a/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd
+++ b/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd
--- a/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd
+++ b/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd