modules/rffe_top/: add rffe module

minicircuits gain ctrl hdl added as RFFE submodules swap RF channels hdl added as RFFE submodule

modules/rffe_top/: add rffe module
minicircuits gain ctrl hdl added as RFFE submodules swap RF channels hdl added as RFFE submodule
825fac9e · José Alvim Berkenbrock · 0046a301 · 825fac9e · 825fac9e · 825fac9e
Commit 825fac9e authored Oct 23, 2012 by José Alvim Berkenbrock
6 changed files
--- a/hdl/modules/rffe_top/Manifest.py
+++ b/hdl/modules/rffe_top/Manifest.py
+#files = [ ".vhd" ];    
+modules = { "local" : [ 
+                        "bpm_swap_ctrl",
+                        "bpm_gain_ctrl"
+                      ] };
\ No newline at end of file
--- a/hdl/modules/rffe_top/bpm_gain_ctrl/Manifest.py
+++ b/hdl/modules/rffe_top/bpm_gain_ctrl/Manifest.py
+files = [   "utilities_package.vhd",
+            "mc_serial_ctrl.vhd",
+   ];                        
\ No newline at end of file
--- a/hdl/modules/rffe_top/bpm_gain_ctrl/mc_serial_ctrl.vhd
+++ b/hdl/modules/rffe_top/bpm_gain_ctrl/mc_serial_ctrl.vhd
+------------------------------------------------------------------------------
+-- Title      : Minicircuits Serial Controller
+------------------------------------------------------------------------------
+-- Author     : Daniel de Oliveira Tavares
+-- Company    : CNPEM LNLS-DIG
+-- Platform   : FPGA-generic
+-------------------------------------------------------------------------------
+-- Description: Automatic Control of Gain in Attenuators
+-------------------------------------------------------------------------------
+-- Notes: Times required by component
+-- fclk = frequency of input clock / g_clkdiv
+-- tclkH = floor(g_clkdiv/2) * period of input clock
+-- tclkL = ceil(g_clkdiv/2) * period of input clock
+-- tLESUP = ceil(g_clkdiv/2) * period of input clock
+-- tLEPW = floor(g_clkdiv/2) * period of input clock
+-- tSDSUP = floor(g_clkdiv/4) * period of input clock
+-- tSDHLD = ceil(g_clkdiv/4) * period of input clock
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012 CNPEM
+-- Licensed under GNU Lesser General Public License (LGPL) v3.0
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author                Description
+-- 2012-01-12  1.0      daniel.tavares        Created
+-- 2012-10-16  1.1      jose.berkenbrock      Names Adpated 
+-------------------------------------------------------------------------------
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+use work.utilities_pkg.all;
+
+entity mc_serial_ctrl is
+generic
+(
+    g_nbits : natural := 6;
+    g_clkdiv : natural := 128
+);
+port
+(
+    clk_i   : in  std_logic;
+    trg_i   : in  std_logic;
+    data_i  : in  std_logic_vector(g_nbits-1 downto 0);
+    clk_o   : out std_logic;
+    data_o  : out std_logic;
+    le_o    : out std_logic;
+    idle_o  : out std_logic
+);
+end mc_serial_ctrl;
+
+architecture rtl of mc_serial_ctrl is
+    signal idle           : std_logic;
+    
+    signal bit_cnt          : unsigned(log2(g_nbits+1)-1 downto 0);
+    constant c_nbits        : unsigned(log2(g_nbits+1)-1 downto 0) := to_unsigned(g_nbits, log2(g_nbits+1));
+    
+    signal clk_cnt          : unsigned(log2(g_clkdiv)-1 downto 0);
+    constant c_clkdiv       : unsigned(log2(g_clkdiv)-1 downto 0) := to_unsigned(g_clkdiv-1, log2(g_clkdiv));
+    constant c_clkdiv_0     : unsigned(log2(g_clkdiv)-1 downto 0) := to_unsigned(0, log2(g_clkdiv));
+
+begin
+    p_outputs: process(clk_i)
+    begin
+        if rising_edge(clk_i) then
+            if trg_i = '1' then
+                idle <= '0';
+                bit_cnt <= c_nbits;
+                clk_cnt <= c_clkdiv_0;
+                le_o <= '0';
+                data_o <= '0';
+                clk_o <= '0';
+            
+            elsif idle = '0' then
+                if clk_cnt = 0 then
+                    if bit_cnt /= 0 then
+                        data_o <= data_i(to_integer(bit_cnt-1));
+                    else
+                        data_o <= '0';
+                    end if;
+                elsif clk_cnt = c_clkdiv/4 then
+                    if bit_cnt = 0 then
+                        le_o <= '1';
+                    else
+                        clk_o <= '1';
+                    end if;
+                elsif clk_cnt = (3*c_clkdiv)/4 then
+                    if bit_cnt = 0 then
+                        le_o <= '0';
+                        idle <= '1';
+                    else
+                        clk_o <= '0';
+                    end if;
+                end if;
+                
+                if clk_cnt = c_clkdiv then
+                    clk_cnt <= c_clkdiv_0;
+                    bit_cnt <= bit_cnt - 1;
+                else
+                    clk_cnt <= clk_cnt + 1;
+                end if;
+            end if;
+        end if;
+    end process;
+    
+    idle_o <= idle;
+    
+end rtl;
--- a/hdl/modules/rffe_top/bpm_gain_ctrl/utilities_package.vhd
+++ b/hdl/modules/rffe_top/bpm_gain_ctrl/utilities_package.vhd
+------------------------------------------------------------------------------
+-- Title      : Utilities Package
+------------------------------------------------------------------------------
+-- Component  : find_msb
+-- Description: 
+------------------------------------------------------------------------------
+-- Component  : data_generator
+-- Description: 
+------------------------------------------------------------------------------
+-- Component  : log2
+-- Description: 
+------------------------------------------------------------------------------
+-- Copyright (c) 2012 CNPEM
+-- Licensed under GNU Lesser General Public License (LGPL) v3.0
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package utilities_pkg is
+
+    function find_msb (signal arg: in std_logic_vector; signal sign: in std_logic) return std_logic_vector;
+    function log2(arg : natural) return natural;
+    
+    component data_generator is
+    generic
+    (
+        g_data_width  : natural range 2 to 48 := 25
+    );
+    port
+    (
+        clk_i           : in std_logic;
+        rst_i           : in std_logic;
+        data_init_i     : in std_logic_vector(g_data_width-1 downto 0);
+        data_step_i     : in std_logic_vector(g_data_width-1 downto 0);
+        niterations_i   : in std_logic_vector(9 downto 0);
+        data_o          : out std_logic_vector(g_data_width-1 downto 0);
+        trg_o           : out std_logic
+    );
+    end component;
+
+end utilities_pkg;
+
+package body utilities_pkg is
+
+    function find_msb (signal arg: in std_logic_vector; signal sign: in std_logic) return std_logic_vector is
+        variable v_index: natural := arg'left;
+        
+    begin
+        while true loop
+            if arg(v_index) = not(sign) then
+                exit;
+            elsif v_index = 0 then
+                exit;
+            end if;
+            v_index := v_index - 1;
+        end loop;
+
+        return std_logic_vector(to_unsigned(v_index,log2(arg'length)+1));
+    end find_msb;
+
+
+    function log2(arg : natural) return natural is
+        variable v_result : natural ;
+        variable v_index  : natural := 0;
+        
+    begin
+        while true loop
+            if 2**v_index >= arg then
+                v_result := v_index;
+                exit ;
+            end if ;
+            v_index := v_index + 1;
+        end loop ;
+      
+        return v_index;    
+    end function;
+
+end utilities_pkg;
+
+
+----------------------------------------------------------------------------------------------
+-- data_generator
+----------------------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+    
+entity data_generator is
+generic
+(
+    g_data_width  : natural range 2 to 48
+);
+port
+(
+    clk_i           : in std_logic;
+    rst_i           : in std_logic;
+    data_init_i     : in std_logic_vector(g_data_width-1 downto 0);
+    data_step_i     : in std_logic_vector(g_data_width-1 downto 0);
+    niterations_i   : in std_logic_vector(9 downto 0);
+    data_o          : out std_logic_vector(g_data_width-1 downto 0);
+    trg_o           : out std_logic
+);
+end data_generator;
+
+architecture rtl of data_generator is
+
+    signal iterations_cnt      : unsigned(9 downto 0);
+    signal data_cnt            : signed(g_data_width-1 downto 0);
+    
+begin
+    p_counter: process(rst_i, clk_i)
+    begin
+        if rst_i = '1' then
+            iterations_cnt <= unsigned(niterations_i);
+            data_cnt <= signed(data_init_i);
+        elsif rising_edge(clk_i) then
+            if iterations_cnt = 0 then
+                trg_o <= '1';
+                data_cnt <= data_cnt + signed(data_step_i);
+                iterations_cnt <= unsigned(niterations_i);
+            else
+                trg_o <= '0';
+                iterations_cnt <= iterations_cnt - 1;
+            end if;
+        end if;
+    end process;
+    
+    data_o <= std_logic_vector(data_cnt);
+end rtl;
\ No newline at end of file
--- a/hdl/modules/rffe_top/bpm_swap_ctrl/Manifest.py
+++ b/hdl/modules/rffe_top/bpm_swap_ctrl/Manifest.py
+files = [ "rf_ch_swap.vhd" ];
\ No newline at end of file
--- a/hdl/modules/rffe_top/bpm_swap_ctrl/rf_ch_swap.vhd
+++ b/hdl/modules/rffe_top/bpm_swap_ctrl/rf_ch_swap.vhd
+------------------------------------------------------------------------------
+-- Title      : RF channels Swapping
+------------------------------------------------------------------------------
+-- Author     : Jos Alvim Berkenbrock
+-- Company    : CNPEM LNLS-DIG
+-- Platform   : FPGA-generic
+-------------------------------------------------------------------------------
+-- Description: This core controls the swapping mechanism for ONE pair of 
+--              channels. It is possible swapping channels inputs @ clk_in_ext 
+--              frequency or stay fixed at direct/inverted/off position.
+--
+--              MODE: 00 turned off 01 direct 10 inverted 11 Swapping
+--
+--              CTRL: b1b0d1d0
+--              This core was developed to Sirus Synchrotron Light Source. 
+--              The BPM RFFE uses HSWA2-30DR+ switches and are controlled by
+--              arrangement of bits in CTRL.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012 CNPEM
+-- Licensed under GNU Lesser General Public License (LGPL) v3.0
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author                Description
+-- 2012-10-18  1.0      jose.berkenbrock      Created 
+-- 2012-10-20  1.1      daniel.tavares
+-------------------------------------------------------------------------------
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity rf_ch_swap is
+generic
+(
+    g_direct   : std_logic_vector(7 downto 0) := "10100101";
+    g_inverted : std_logic_vector(7 downto 0) := "01011010"
+);
+port(
+  clk_i     :    in std_logic;
+  rst_i     :    in std_logic;
+  en_swap_i :    in std_logic;
+  mode_i    :    in std_logic_vector(1 downto 0);
+  ctrl_o    :    out std_logic_vector(7 downto 0));
+end rf_ch_swap;
+
+architecture rtl of rf_ch_swap is
+
+--signal s_mode     :    std_logic_vector(1 downto 0);
+signal ctrl     :    std_logic_vector(7 downto 0);
+--signal ctrl_aux :    std_logic_vector(7 downto 0);
+--signal ctrl_old :    std_logic_vector(7 downto 0);
+--signal s_bit      :    std_logic;
+
+begin
+--------------------------------
+-- Input Register
+--------------------------------
+--  p_reg_mode : process(rst_i, clk_i)
+--  begin
+--    if rst_i = '1' then
+--      s_mode <= (others => '0');
+--    elsif rising_edge(clk_i) then
+--      s_mode <= mode_i;
+--    else s_mode <= s_mode;
+--    end if;
+--  end process p_reg_mode;
+--------------------------------
+-- Swapping Process
+--------------------------------
+  p_swap : process(clk_i,rst_i)
+  begin
+---------------------------------------------------------------
+--    if rst_i = '1' then
+--      s_bit <= '0';
+--      ctrl_aux <= "10100101";
+--      ctrl <= "10100101";
+--    elsif rising_edge(clk_i) then
+--      s_bit <= not s_bit;
+--    else s_bit <= s_bit;
+--    end if;
+
+---------------------------------------------------------------
+    if rst_i = '1' then
+     --ctrl_old <= "10100101";             -- initialize in direct channels
+     --s_bit <= '0';
+       ctrl <= "00000000";
+   elsif rising_edge(clk_i) then
+     if mode_i = "11" then                 -- crossed Swapping
+     --  ctrl <= not ctrl;
+       if en_swap_i = '0' then
+          ctrl <= g_direct;
+       else 
+          ctrl <= g_inverted;
+       end if;
+     elsif mode_i = "10" then              -- inverted
+       ctrl <= g_inverted;
+     elsif mode_i = "01" then              -- direct
+       ctrl <= g_direct;
+     else
+       ctrl <= (others=>'0');            -- Swapping off
+     end if;
+     --ctrl_old <= ctrl;
+ end if;
+--  ctrl <= "10100101" when s_bit = '1' else "01011010";
+--  with s_bit select
+--  ctrl <= "10100101" when '0',
+--            "01011010" when others;
+---------------------------------------------------------------
+  end process p_swap;
+  
+---------------------------------------------------------------
+--    with s_bit select
+--    ctrl_aux <= "10100101" when '0',
+--                  "01011010" when '1';
+--                  ctrl_aux when others;
+--
+--    with s_mode select
+--    ctrl <= "00000000" when "00",
+--              "10100101" when "01",
+--              "01011010" when "10",
+--              ctrl_aux when "11";
+--              ctrl when others;
+--------------------------------
+-- Output Register
+--------------------------------
+  p_reg_ctrl : process(rst_i, clk_i)
+  begin
+    if rst_i = '1' then
+      ctrl_o <= (others => '0');            -- rst_i = 1 => Swapping off
+--      ctrl_old <= "00000000"; 
+    elsif rising_edge(clk_i) then
+      ctrl_o <= ctrl;
+--      ctrl_old <= ctrl;
+    end if;
+  end process p_reg_ctrl;
+
+end rtl;
\ No newline at end of file