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Beam Positoning Monitor - Gateware
Commit 7efbf4c3 authored by Lucas Russo's avatar Lucas Russo
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hdl/modules/dbe_wishbone/*: update FMC ADC modules 

As the previous commit changed the interface of the
ADC module, we update them here
parent ff801040
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hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd
View file @ 7efbf4c3
......@@ -447,6 +447,13 @@ package dbe_wishbone_pkg is
--FMC Present status
fmc_prsnt_m2c_l_i : in std_logic;
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i : in std_logic := '0';
fmc_ext_ref_clk2x_i : in std_logic := '0';
fmc_ext_ref_mmcm_locked_i : in std_logic := '0';
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
......@@ -599,6 +606,13 @@ package dbe_wishbone_pkg is
--FMC Present status
fmc_prsnt_m2c_l_i : in std_logic;
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i : in std_logic := '0';
fmc_ext_ref_clk2x_i : in std_logic := '0';
fmc_ext_ref_mmcm_locked_i : in std_logic := '0';
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
......@@ -750,6 +764,13 @@ package dbe_wishbone_pkg is
fmc_led2_o : out std_logic;
fmc_led3_o : out std_logic;
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i : in std_logic := '0';
fmc_ext_ref_clk2x_i : in std_logic := '0';
fmc_ext_ref_mmcm_locked_i : in std_logic := '0';
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
......@@ -901,6 +922,13 @@ package dbe_wishbone_pkg is
fmc_led2_o : out std_logic;
fmc_led3_o : out std_logic;
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i : in std_logic := '0';
fmc_ext_ref_clk2x_i : in std_logic := '0';
fmc_ext_ref_mmcm_locked_i : in std_logic := '0';
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
......
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd
View file @ 7efbf4c3
......@@ -161,6 +161,13 @@ port
fmc_led2_o : out std_logic;
fmc_led3_o : out std_logic;
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i : in std_logic := '0';
fmc_ext_ref_clk2x_i : in std_logic := '0';
fmc_ext_ref_mmcm_locked_i : in std_logic := '0';
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
......@@ -331,6 +338,9 @@ architecture rtl of wb_fmc130m_4ch is
signal adc_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_data : std_logic_vector(c_num_adc_bits*c_num_adc_channels-1 downto 0);
-- Optional reference clock
signal adc_ext_glob_clk_int : t_adc_clk_chain_glob;
-- ADC Reset signals
signal adc_clk_div_rst_int : std_logic;
signal adc_clk_div_rst_int_p : std_logic;
......@@ -966,6 +976,11 @@ begin
adc_in_i => adc_in_dummy,
adc_in_sdr_i => adc_in,
-----------------------------
-- Optional External Global Clock ports
-----------------------------
adc_ext_glob_clk_i => adc_ext_glob_clk_int,
-----------------------------
-- ADC Delay signals
-----------------------------
......@@ -997,6 +1012,11 @@ begin
-- General status board pins
fmc_mmcm_lock_o <= mmcm_adc_locked;
-- Optional reference clock
adc_ext_glob_clk_int.adc_clk_bufg <= fmc_ext_ref_clk_i;
adc_ext_glob_clk_int.adc_clk2x_bufg <= fmc_ext_ref_clk2x_i;
adc_ext_glob_clk_int.mmcm_adc_locked <= fmc_ext_ref_mmcm_locked_i;
-- ADC data for internal use
gen_adc_data_int : for i in 0 to c_num_adc_channels-1 generate
--adc_clk_int(i) <= adc_out(i).adc_clk;
......
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/xwb_fmc130m_4ch.vhd
View file @ 7efbf4c3
......@@ -139,6 +139,13 @@ port
fmc_led2_o : out std_logic;
fmc_led3_o : out std_logic;
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i : in std_logic := '0';
fmc_ext_ref_clk2x_i : in std_logic := '0';
fmc_ext_ref_mmcm_locked_i : in std_logic := '0';
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
......@@ -305,6 +312,13 @@ begin
fmc_led2_o => fmc_led2_o,
fmc_led3_o => fmc_led3_o,
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i => fmc_ext_ref_clk_i,
fmc_ext_ref_clk2x_i => fmc_ext_ref_clk2x_i,
fmc_ext_ref_mmcm_locked_i => fmc_ext_ref_mmcm_locked_i,
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
......
hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd
View file @ 7efbf4c3
......@@ -163,6 +163,13 @@ port
--FMC Present status
fmc_prsnt_m2c_l_i : in std_logic := '0';
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i : in std_logic := '0';
fmc_ext_ref_clk2x_i : in std_logic := '0';
fmc_ext_ref_mmcm_locked_i : in std_logic := '0';
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
......@@ -341,6 +348,9 @@ architecture rtl of wb_fmc516 is
signal adc_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_data : std_logic_vector(c_num_adc_bits*c_num_adc_channels-1 downto 0);
-- Optional reference clock
signal adc_ext_glob_clk_int : t_adc_clk_chain_glob;
-- ADC Reset signals
signal adc_clk_div_rst_int : std_logic;
signal adc_clk_div_rst_int_p : std_logic;
......@@ -1027,6 +1037,11 @@ begin
adc_in_i => adc_in,
adc_in_sdr_i => adc_in_sdr_dummy,
-----------------------------
-- Optional External Global Clock ports
-----------------------------
adc_ext_glob_clk_i => adc_ext_glob_clk_int,
-----------------------------
-- ADC Delay signals
-----------------------------
......@@ -1057,6 +1072,11 @@ begin
-- General status board pins
fmc_mmcm_lock_o <= mmcm_adc_locked;
-- Optional reference clock
adc_ext_glob_clk_int.adc_clk_bufg <= fmc_ext_ref_clk_i;
adc_ext_glob_clk_int.adc_clk2x_bufg <= fmc_ext_ref_clk2x_i;
adc_ext_glob_clk_int.mmcm_adc_locked <= fmc_ext_ref_mmcm_locked_i;
-- ADC data for internal use
gen_adc_data_int : for i in 0 to c_num_adc_channels-1 generate
--adc_clk_int(i) <= adc_out(i).adc_clk;
......
hdl/modules/dbe_wishbone/wb_fmc516/xwb_fmc516.vhd
View file @ 7efbf4c3
......@@ -141,6 +141,13 @@ port
--FMC Present status
fmc_prsnt_m2c_l_i : in std_logic;
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i : in std_logic := '0';
fmc_ext_ref_clk2x_i : in std_logic := '0';
fmc_ext_ref_mmcm_locked_i : in std_logic := '0';
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
......@@ -306,6 +313,13 @@ begin
--FMC Present status
fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_l_i,
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i => fmc_ext_ref_clk_i,
fmc_ext_ref_clk2x_i => fmc_ext_ref_clk2x_i,
fmc_ext_ref_mmcm_locked_i => fmc_ext_ref_mmcm_locked_i,
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
......
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