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Beam Positoning Monitor - Gateware
Commit 42a5a422 authored by Vitor Finotti's avatar Vitor Finotti
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Added pulse detected outputs to receiver and respective constraints for the FMC connector

parent c4fb90b8
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Showing with 32 additions and 2 deletions
hdl/top/afc_v3/vivado/test_trigger/rcv/test_trigger_rcv.vhd
View file @ 42a5a422
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
-- Author : aylons <aylons@LNLS190> -- Author : aylons <aylons@LNLS190>
-- Company : -- Company :
-- Created : 2015-11-11 -- Created : 2015-11-11
-- Last update: 2016-01-22 -- Last update: 2016-04-25
-- Platform : -- Platform :
-- Standard : VHDL'93/02 -- Standard : VHDL'93/02
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -51,7 +51,8 @@ entity test_trigger_rcv is ...@@ -51,7 +51,8 @@ entity test_trigger_rcv is
sys_clk_p_i : in std_logic; sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic; sys_clk_n_i : in std_logic;
trigger_i : in std_logic_vector(7 downto 0); trigger_i : in std_logic_vector(7 downto 0);
direction_o : out std_logic_vector(7 downto 0) direction_o : out std_logic_vector(7 downto 0);
pulse_o : out std_logic_vector(7 downto 0)
); );
end test_trigger_rcv; end test_trigger_rcv;
...@@ -240,6 +241,9 @@ begin ...@@ -240,6 +241,9 @@ begin
end generate gen_trigger; end generate gen_trigger;
-- Connect pulses signals to the output
pulse_o <= pulse;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- State Machine -- State Machine
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
......
hdl/top/afc_v3/vivado/test_trigger/rcv/test_trigger_rcv.xdc
View file @ 42a5a422
...@@ -62,3 +62,29 @@ set_property IOSTANDARD LVCMOS15 [get_ports {direction_o[6]}] ...@@ -62,3 +62,29 @@ set_property IOSTANDARD LVCMOS15 [get_ports {direction_o[6]}]
set_property PACKAGE_PIN AP9 [get_ports {direction_o[7]}] set_property PACKAGE_PIN AP9 [get_ports {direction_o[7]}]
set_property IOSTANDARD LVCMOS15 [get_ports {direction_o[7]}] set_property IOSTANDARD LVCMOS15 [get_ports {direction_o[7]}]
#Pulses output to FMC
set_property PACKAGE_PIN L5 [get_ports {pulse_o[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {pulse_o[0]}]
set_property PACKAGE_PIN K5 [get_ports {pulse_o[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {pulse_o[1]}]
set_property PACKAGE_PIN K3 [get_ports {pulse_o[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {pulse_o[2]}]
set_property PACKAGE_PIN K2 [get_ports {pulse_o[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {pulse_o[3]}]
set_property PACKAGE_PIN F3 [get_ports {pulse_o[4]}]
set_property IOSTANDARD LVCMOS15 [get_ports {pulse_o[4]}]
set_property PACKAGE_PIN F2 [get_ports {pulse_o[5]}]
set_property IOSTANDARD LVCMOS15 [get_ports {pulse_o[5]}]
set_property PACKAGE_PIN J4 [get_ports {pulse_o[6]}]
set_property IOSTANDARD LVCMOS15 [get_ports {pulse_o[6]}]
set_property PACKAGE_PIN J3 [get_ports {pulse_o[7]}]
set_property IOSTANDARD LVCMOS15 [get_ports {pulse_o[7]}]
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