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Commit 339a9d9d authored by Lucas Russo's avatar Lucas Russo
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ethmac/: using ethmac from openrisc project 

Also, wrappers were created to adhere to
some coding guidelines and to convert between
Wishbone B4 (pipelined) <->  Wishbone B2
parent ec013494
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hdl/modules/eth_mac/eth_rxethmac.v deleted 100644 → 0
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hdl/modules/eth_mac/eth_wishbone.v deleted 100644 → 0
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hdl/modules/eth_mac/ethmac.v deleted 100644 → 0
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hdl/modules/eth_mac/wb_eth_mac.vhd deleted 100644 → 0
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library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
entity wb_eth_mac is
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
TX_FIFO_DATA_WIDTH : natural;
TX_FIFO_DEPTH : natural;
TX_FIFO_CNT_WIDTH : natural;
RX_FIFO_DATA_WIDTH : natural;
RX_FIFO_DEPTH : natural;
RX_FIFO_CNT_WIDTH : natural
);
port(
-- WISHBONE common
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
-- WISHBONE slave
wb_adr_i: in std_logic_vector(11 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_dat_o: in std_logic_vector(31 downto 0);
wb_sel_i,
wb_we_i,
wb_cyc_i,
wb_stb_i,
wb_ack_o,
wb_err_o,
-- WISHBONE master
m_wb_adr_o: in std_logic_vector(31 downto 0);
m_wb_sel_o,
m_wb_we_o,
m_wb_dat_o: in std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_cyc_o,
m_wb_stb_o,
m_wb_ack_i,
m_wb_err_i,
m_wb_cti_o (2 downto 0),
m_wb_bte_o (1 downto 0),
int_o,
-- TX
mtx_clk_pad_i,
mtxd_pad_o,
mtxen_pad_o,
mtxerr_pad_o,
-- RX
mrx_clk_pad_i,
mrxd_pad_i,
mrxdv_pad_i,
mrxerr_pad_i,
mcoll_pad_i,
mcrs_pad_i,
-- MIIM
mdc_pad_o,
md_pad_i,
md_pad_o,
md_padoe_o,
-- Bist
-- debug chain signals
mbist_si_i, -- bist scan serial in
mbist_so_o, -- bist scan serial out
mbist_ctrl_i -- bist chain shift control
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
pad_cs_o : out std_logic_vector(7 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
pad_miso_i : in std_logic;
pad_miosio_b : inout std_logic
);
end wb_eth_mac;
architecture rtl of wb_eth_mac is
component spi_top
generic (
g_three_wire_mode : integer := 0
);
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_int_o : out std_logic;
ss_pad_o : out std_logic_vector(7 downto 0);
sclk_pad_o : out std_logic;
mosi_pad_o : out std_logic;
miso_pad_i : in std_logic;
miosio_pad_b : inout std_logic);
end component;
signal rst : std_logic;
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
begin
resized_addr(4 downto 0) <= wb_adr_i;
resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0');
U_Adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => BYTE,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => resized_addr,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o,
sl_int_o => wb_int_o,
sl_err_o => wb_err_o);
rst <= not rst_n_i;
Wrapped_SPI : spi_top -- byte-aligned
generic map (
g_three_wire_mode => g_three_wire_mode
)
port map (
wb_clk_i => clk_sys_i,
wb_rst_i => rst,
wb_adr_i => wb_in.adr(4 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_cyc_i => wb_in.cyc,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_err_o => wb_out.err,
wb_int_o => wb_out.int,
ss_pad_o => pad_cs_o,
sclk_pad_o => pad_sclk_o,
mosi_pad_o => pad_mosi_o,
miso_pad_i => pad_miso_i,
miosio_pad_b => pad_miosio_b);
end rtl;
hdl/modules/ethmac/Manifest.py 0 → 100644
View file @ 339a9d9d
files = [
"eth_random.v", "eth_txcounters.v", "eth_clockgen.v",
"eth_receivecontrol.v",
"eth_txethmac.v", "eth_cop.v", "eth_registers.v", "eth_txstatem.v",
"eth_crc.v", "eth_register.v", "eth_wishbone.v", "eth_defines.v",
"eth_rxaddrcheck.v", "eth_fifo.v", "eth_rxcounters.v", "timescale.v",
"eth_maccontrol.v", "eth_rxethmac.v", "ethmac_defines.v",
"eth_rxstatem.v", "eth_macstatus.v", "eth_shiftreg.v",
"xilinx_dist_ram_16x32.v", "ethmac.v", "eth_spram_256x32.v",
"eth_miim.v", "eth_top.v", "eth_outputcontrol.v", "eth_transmitcontrol.v",
"wb_ethmac.vhd", "xwb_ethmac.vhd", "ethmac_pkg.vhd" ];
hdl/modules/ethmac/README 0 → 100644
View file @ 339a9d9d
10/100MBps ethernet MAC core
This is based on the core from OpenCores, but heavily modified and improved to provide better bus usage, and buffer configurability.
See the include file, include/ethmac_defines.v for options.
hdl/modules/eth_mac/eth_clockgen.v → hdl/modules/ethmac/eth_clockgen.v
View file @ 339a9d9d
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
//// eth_clockgen.v //// //// eth_clockgen.v ////
//// //// //// ////
//// This file is part of the Ethernet IP core project //// //// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac //// //// http://www.opencores.org/project,ethmac ////
//// //// //// ////
//// Author(s): //// //// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) //// //// - Igor Mohor (igorM@opencores.org) ////
...@@ -70,6 +70,8 @@ ...@@ -70,6 +70,8 @@
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc); module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
parameter Tp=1;
input Clk; // Input clock (Host clock) input Clk; // Input clock (Host clock)
input Reset; // Reset signal input Reset; // Reset signal
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0]) input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
......
hdl/modules/eth_mac/eth_crc.v → hdl/modules/ethmac/eth_crc.v
View file @ 339a9d9d
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
//// eth_crc.v //// //// eth_crc.v ////
//// //// //// ////
//// This file is part of the Ethernet IP core project //// //// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac //// //// http://www.opencores.org/project,ethmac ////
//// //// //// ////
//// Author(s): //// //// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) //// //// - Igor Mohor (igorM@opencores.org) ////
...@@ -79,6 +79,8 @@ ...@@ -79,6 +79,8 @@
module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError); module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
parameter Tp = 1;
input Clk; input Clk;
input Reset; input Reset;
input [3:0] Data; input [3:0] Data;
......
hdl/modules/eth_mac/ethmac_defines.v → hdl/modules/ethmac/eth_defines.v
View file @ 339a9d9d
////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////
//// //// //// ////
//// ethmac_defines.v //// //// eth_defines.v ////
//// //// //// ////
//// This file is part of the Ethernet IP core project //// //// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac //// //// http://www.opencores.org/projects/ethmac/ ////
//// //// //// ////
//// Author(s): //// //// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) //// //// - Igor Mohor (igorM@opencores.org) ////
...@@ -38,9 +38,6 @@ ...@@ -38,9 +38,6 @@
//// //// //// ////
////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////
// //
// Renamed from eth_defines.v to ethmac_defines.v to fit better into
// OpenCores defined project structure 2011-08-04 olof@opencores.org
//
// CVS Revision History // CVS Revision History
// //
// $Log: not supported by cvs2svn $ // $Log: not supported by cvs2svn $
...@@ -222,7 +219,7 @@ ...@@ -222,7 +219,7 @@
`define ETH_HASH1_ADR 8'h13 // 0x4C `define ETH_HASH1_ADR 8'h13 // 0x4C
`define ETH_TX_CTRL_ADR 8'h14 // 0x50 `define ETH_TX_CTRL_ADR 8'h14 // 0x50
`define ETH_RX_CTRL_ADR 8'h15 // 0x54 `define ETH_RX_CTRL_ADR 8'h15 // 0x54
`define ETH_DBG_ADR 8'h16 // 0x58
`define ETH_MODER_DEF_0 8'h00 `define ETH_MODER_DEF_0 8'h00
`define ETH_MODER_DEF_1 8'hA0 `define ETH_MODER_DEF_1 8'hA0
...@@ -330,3 +327,19 @@ ...@@ -330,3 +327,19 @@
`define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH `define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH
`define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH `define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH
// WISHBONE interface is Revision B3 compliant (uncomment when needed)
//`define ETH_WISHBONE_B3
// Following defines are needed when eth_cop.v is used. Otherwise they may be deleted.
`define ETH_BASE 32'hd0000000
`define ETH_WIDTH 32'h800
`define MEMORY_BASE 32'h2000
`define MEMORY_WIDTH 32'h10000
`define M1_ADDRESSED_S1 ( (m1_wb_adr_i >= `ETH_BASE) & (m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
`define M1_ADDRESSED_S2 ( (m1_wb_adr_i >= `MEMORY_BASE) & (m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
`define M2_ADDRESSED_S1 ( (m2_wb_adr_i >= `ETH_BASE) & (m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
`define M2_ADDRESSED_S2 ( (m2_wb_adr_i >= `MEMORY_BASE) & (m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
// Previous defines are only needed for eth_cop.v
hdl/modules/eth_mac/eth_maccontrol.v → hdl/modules/ethmac/eth_maccontrol.v
View file @ 339a9d9d
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
//// eth_maccontrol.v //// //// eth_maccontrol.v ////
//// //// //// ////
//// This file is part of the Ethernet IP core project //// //// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac //// //// http://www.opencores.org/project,ethmac ////
//// //// //// ////
//// Author(s): //// //// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) //// //// - Igor Mohor (igorM@opencores.org) ////
...@@ -94,6 +94,8 @@ module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxS ...@@ -94,6 +94,8 @@ module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxS
); );
parameter Tp = 1;
input MTxClk; // Transmit clock (from PHY) input MTxClk; // Transmit clock (from PHY)
input MRxClk; // Receive clock (from PHY) input MRxClk; // Receive clock (from PHY)
......
hdl/modules/eth_mac/eth_macstatus.v → hdl/modules/ethmac/eth_macstatus.v
View file @ 339a9d9d
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
//// eth_macstatus.v //// //// eth_macstatus.v ////
//// //// //// ////
//// This file is part of the Ethernet IP core project //// //// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac //// //// http://www.opencores.org/project,ethmac ////
//// //// //// ////
//// Author(s): //// //// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) //// //// - Igor Mohor (igorM@opencores.org) ////
...@@ -126,6 +126,8 @@ module eth_macstatus( ...@@ -126,6 +126,8 @@ module eth_macstatus(
parameter Tp = 1;
input MRxClk; input MRxClk;
input Reset; input Reset;
......
hdl/modules/eth_mac/eth_miim.v → hdl/modules/ethmac/eth_miim.v
View file @ 339a9d9d
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
//// eth_miim.v //// //// eth_miim.v ////
//// //// //// ////
//// This file is part of the Ethernet IP core project //// //// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac //// //// http://www.opencores.org/project,ethmac ////
//// //// //// ////
//// Author(s): //// //// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) //// //// - Igor Mohor (igorM@opencores.org) ////
...@@ -135,6 +135,8 @@ output WCtrlDataStart; // This signals resets the WCTRLDATA bit in th ...@@ -135,6 +135,8 @@ output WCtrlDataStart; // This signals resets the WCTRLDATA bit in th
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
parameter Tp = 1;
reg Nvalid; reg Nvalid;
reg EndBusy_d; // Pre-end Busy signal reg EndBusy_d; // Pre-end Busy signal
......
hdl/modules/eth_mac/eth_outputcontrol.v → hdl/modules/ethmac/eth_outputcontrol.v
View file @ 339a9d9d
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
//// eth_outputcontrol.v //// //// eth_outputcontrol.v ////
//// //// //// ////
//// This file is part of the Ethernet IP core project //// //// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac //// //// http://www.opencores.org/project,ethmac ////
//// //// //// ////
//// Author(s): //// //// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) //// //// - Igor Mohor (igorM@opencores.org) ////
...@@ -70,6 +70,8 @@ ...@@ -70,6 +70,8 @@
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn); module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
parameter Tp = 1;
input Clk; // Host Clock input Clk; // Host Clock
input Reset; // General Reset input Reset; // General Reset
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress) input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
......
hdl/modules/eth_mac/eth_random.v → hdl/modules/ethmac/eth_random.v
View file @ 339a9d9d
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
//// eth_random.v //// //// eth_random.v ////
//// //// //// ////
//// This file is part of the Ethernet IP core project //// //// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac //// //// http://www.opencores.org/project,ethmac ////
//// //// //// ////
//// Author(s): //// //// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) //// //// - Igor Mohor (igorM@opencores.org) ////
...@@ -82,6 +82,8 @@ ...@@ -82,6 +82,8 @@
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt, module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
RandomEq0, RandomEqByteCnt); RandomEq0, RandomEqByteCnt);
parameter Tp = 1;
input MTxClk; input MTxClk;
input Reset; input Reset;
input StateJam; input StateJam;
......
hdl/modules/eth_mac/eth_receivecontrol.v → hdl/modules/ethmac/eth_receivecontrol.v
View file @ 339a9d9d
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
//// eth_receivecontrol.v //// //// eth_receivecontrol.v ////
//// //// //// ////
//// This file is part of the Ethernet IP core project //// //// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac //// //// http://www.opencores.org/project,ethmac ////
//// //// //// ////
//// Author(s): //// //// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) //// //// - Igor Mohor (igorM@opencores.org) ////
...@@ -84,6 +84,8 @@ module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, Rx ...@@ -84,6 +84,8 @@ module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, Rx
RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
); );
parameter Tp = 1;
input MTxClk; input MTxClk;
input MRxClk; input MRxClk;
......
hdl/modules/eth_mac/eth_register.v → hdl/modules/ethmac/eth_register.v
View file @ 339a9d9d
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
//// eth_register.v //// //// eth_register.v ////
//// //// //// ////
//// This file is part of the Ethernet IP core project //// //// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac //// //// http://www.opencores.org/project,ethmac ////
//// //// //// ////
//// Author(s): //// //// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) //// //// - Igor Mohor (igorM@opencores.org) ////
......
hdl/modules/ethmac/eth_rxethmac.v 0 → 100644
View file @ 339a9d9d
This diff is collapsed.
hdl/modules/eth_mac/eth_rxstatem.v → hdl/modules/ethmac/eth_rxstatem.v
View file @ 339a9d9d
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
//// eth_rxstatem.v //// //// eth_rxstatem.v ////
//// //// //// ////
//// This file is part of the Ethernet IP core project //// //// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac //// //// http://www.opencores.org/project,ethmac ////
//// //// //// ////
//// Author(s): //// //// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) //// //// - Igor Mohor (igorM@opencores.org) ////
...@@ -90,6 +90,8 @@ module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitti ...@@ -90,6 +90,8 @@ module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitti
StateDrop StateDrop
); );
parameter Tp = 1;
input MRxClk; input MRxClk;
input Reset; input Reset;
input MRxDV; input MRxDV;
...@@ -133,8 +135,8 @@ assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1); ...@@ -133,8 +135,8 @@ assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame); assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 & assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 &
MRxDEqD | StateData0 & ByteCntMaxFrame); MRxDEqD | StateData0 & ByteCntMaxFrame);
// Rx State Machine // Rx State Machine
always @ (posedge MRxClk or posedge Reset) always @ (posedge MRxClk or posedge Reset)
......
hdl/modules/ethmac/eth_wishbone.v 0 → 100644
View file @ 339a9d9d
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hdl/modules/ethmac/ethmac.v 0 → 100644
View file @ 339a9d9d
This diff is collapsed.
hdl/modules/ethmac/ethmac_defines.v 0 → 100755
View file @ 339a9d9d
This diff is collapsed.
hdl/modules/ethmac/ethmac_pkg.vhd 0 → 100644
View file @ 339a9d9d
This diff is collapsed.
hdl/modules/ethmac/wb_ethmac.vhd 0 → 100644
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hdl/modules/ethmac/xwb_ethmac.vhd 0 → 100644
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