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Beam Positoning Monitor - Gateware
Commit 32d1b8ce authored by Lucas Russo's avatar Lucas Russo
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emb-sw/*: small fixes and indentation issues

parent 46b14fbd
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Showing with 226 additions and 175 deletions
embedded-sw/boards/ml605/board.h
View file @ 32d1b8ce
......@@ -62,6 +62,10 @@
#define GEN_LED_GPIO_ID 0
#define GEN_BUTTON_GPIO_ID 1
#define FMC150_ID 0
#define FMC516_ID 0
#define TICS_ID 0
/*
* IDs of some FMC516 components
*/
......
embedded-sw/dev/dma.c
View file @ 32d1b8ce
#include "board.h" // Board definitions: DMA device structure
#include "dma.h" // DMA device functions
#include "memmgr.h"
// Global DMA handler.
//dma_t *dma;
......@@ -7,48 +8,48 @@ dma_t **dma;
int dma_init(void)
{
int i;
struct dev_node *dev_p = 0;
int i;
struct dev_node *dev_p = 0;
if (!dma_devl->devices)
return -1;
if (!dma_devl->devices)
return -1;
// get all base addresses
dma = (dma_t **) memmgr_alloc(sizeof(dma_t *)*dma_devl->size);
// get all base addresses
dma = (dma_t **) memmgr_alloc(sizeof(dma_t *)*dma_devl->size);
//dbg_print("> dma size: %d\n", dma_devl->size);
//dbg_print("> dma size: %d\n", dma_devl->size);
for (i = 0, dev_p = dma_devl->devices; i < dma_devl->size;
++i, dev_p = dev_p->next) {
dma[i] = (dma_t *) dev_p->base;
//dbg_print("> dma addr[%d]: %08X\n", i, gpio[i]);
}
//dma = (dma_t *)dma_devl->devices->base;//BASE_GPIO;
return 0;
for (i = 0, dev_p = dma_devl->devices; i < dma_devl->size;
++i, dev_p = dev_p->next) {
dma[i] = (dma_t *) dev_p->base;
//dbg_print("> dma addr[%d]: %08X\n", i, gpio[i]);
}
//dma = (dma_t *)dma_devl->devices->base;//BASE_GPIO;
return 0;
}
/* DMA user interface definition */
int read_is_addr(unsigned int id)
{
return dma[id]->RD_ADDR;
return dma[id]->RD_ADDR;
}
void write_is_addr(unsigned int id, int addr)
{
dma[id]->WR_ADDR = (uint32_t)addr;
dma[id]->WR_ADDR = (uint32_t)addr;
}
int read_strd(unsigned int id)
{
return dma[id]->RD_STRD;
return dma[id]->RD_STRD;
}
void write_strd(unsigned int id, int strd)
{
dma[id]->WR_STRD = (uint32_t) strd;
dma[id]->WR_STRD = (uint32_t) strd;
}
int read_tr_count(unsigned int id)
{
return dma[id]->TR_COUNT;
return dma[id]->TR_COUNT;
}
embedded-sw/dev/ethmac_adapt.c
View file @ 32d1b8ce
......@@ -2,6 +2,7 @@
#include "board.h"
#include "ethmac_adapt.h" // Etherbone MAC Adapter device functions
#include "memmgr.h"
#include "debug_print.h"
// Global handler.
......@@ -9,47 +10,47 @@ ethmac_adapt_t **ethmac_adapt;
int ethmac_adapt_init(void)
{
int i;
struct dev_node *dev_p = 0;
int i;
struct dev_node *dev_p = 0;
if (!ethmac_adapt_devl->devices)
return -1;
if (!ethmac_adapt_devl->devices)
return -1;
// get all base addresses
ethmac_adapt = (ethmac_adapt_t **) memmgr_alloc(sizeof(ethmac_adapt_t *)*ethmac_adapt_devl->size);
// get all base addresses
ethmac_adapt = (ethmac_adapt_t **) memmgr_alloc(sizeof(ethmac_adapt_t *)*ethmac_adapt_devl->size);
//dbg_print("> ethmac_adapt size: %d\n", ethmac_adapt_devl->size);
//dbg_print("> ethmac_adapt size: %d\n", ethmac_adapt_devl->size);
for (i = 0, dev_p = ethmac_adapt_devl->devices; i < ethmac_adapt_devl->size;
++i, dev_p = dev_p->next) {
ethmac_adapt[i] = (ethmac_adapt_t *) dev_p->base;
//dbg_print("> dma addr[%d]: %08X\n", i, gpio[i]);
}
//ethmac_adapt = (ethmac_adapt_t *)ethmac_adapt_devl->devices->base;//BASE_GPIO;
return 0;
for (i = 0, dev_p = ethmac_adapt_devl->devices; i < ethmac_adapt_devl->size;
++i, dev_p = dev_p->next) {
ethmac_adapt[i] = (ethmac_adapt_t *) dev_p->base;
//dbg_print("> dma addr[%d]: %08X\n", i, gpio[i]);
}
//ethmac_adapt = (ethmac_adapt_t *)ethmac_adapt_devl->devices->base;//BASE_GPIO;
return 0;
}
int ethmac_adapt_set_base(unsigned int id, unsigned int base_rx, unsigned int base_tx)
{
ethmac_adapt[id]->base_rx = base_rx;
ethmac_adapt[id]->base_tx = base_tx;
ethmac_adapt[id]->base_rx = base_rx;
ethmac_adapt[id]->base_tx = base_tx;
return 0;
return 0;
}
int ethmac_adapt_set_length(unsigned int id, unsigned int length)
{
ethmac_adapt[id]->length = length;
ethmac_adapt[id]->length = length;
return 0;
return 0;
}
int ethmac_adapt_go(unsigned int id)
{
// write anything to trigger a transaction
ethmac_adapt[id]->doit = 1;
// write anything to trigger a transaction
ethmac_adapt[id]->doit = 1;
return 0;
return 0;
}
......
embedded-sw/dev/gpio.c
View file @ 32d1b8ce
#include "board.h" // Board definitions: GPIO device structure
#include "gpio.h" // GPIO device functions
#include "memmgr.h"
#include "debug_print.h"
// Global GPIO handler.
gpio_t **gpio;
int gpio_init()
{
int i;
struct dev_node *dev_p = 0;
int i;
struct dev_node *dev_p = 0;
if (!gpio_devl->devices)
return -1;
if (!gpio_devl->devices)
return -1;
// get all base addresses
gpio = (gpio_t **) memmgr_alloc(sizeof(gpio_t *)*gpio_devl->size);
// get all base addresses
gpio = (gpio_t **) memmgr_alloc(sizeof(gpio_t *)*gpio_devl->size);
//dbg_print("> gpio size: %d\n", gpio_devl->size);
for (i = 0, dev_p = gpio_devl->devices; i < gpio_devl->size;
++i, dev_p = dev_p->next) {
gpio[i] = (gpio_t *) dev_p->base;
dbg_print("> gpio addr[%d]: %08X\n", i, dev_p->base);
}
for (i = 0, dev_p = gpio_devl->devices; i < gpio_devl->size;
++i, dev_p = dev_p->next) {
gpio[i] = (gpio_t *) dev_p->base;
//dbg_print("> gpio addr[%d]: %08X\n", i, gpio[i]);
}
//gpio = (gpio_t *)gpio_devl->devices->base;//BASE_GPIO;
return 0;
dbg_print("> gpio size: %d\n", gpio_devl->size);
//gpio = (gpio_t *)gpio_devl->devices->base;//BASE_GPIO;
return 0;
}
int gpio_exit()
{
// free gpio structure
memmgr_free(gpio);
// free gpio structure
memmgr_free(gpio);
return 0;
return 0;
}
/* GPIO user interface definition */
void gpio_out(unsigned int id, int pin, int val)
{
if(val)
gpio[id]->SODR = (1<<pin);
else
gpio[id]->CODR = (1<<pin);
if(val)
gpio[id]->SODR = (1<<pin);
else
gpio[id]->CODR = (1<<pin);
}
void gpio_dir(unsigned int id, int pin, int val)
{
if(val)
gpio[id]->DDR |= (1<<pin);
else
gpio[id]->DDR &= ~(1<<pin);
if(val)
gpio[id]->DDR |= (1<<pin);
else
gpio[id]->DDR &= ~(1<<pin);
}
int gpio_in(unsigned int id, int pin)
{
return gpio[id]->PSR & (1<<pin) ? 1 : 0;
return gpio[id]->PSR & (1<<pin) ? 1 : 0;
}
embedded-sw/dev/onewire.c
View file @ 32d1b8ce
......@@ -6,119 +6,122 @@
#include "board.h" // Board definitions: SPI device structure
#include "onewire.h" // SPI device functions
#include "memmgr.h" // malloc and free clones
#include "debug_print.h"
// Global SPI handler.
owr_t **owr;
int owr_init(void)
{
int i;
struct dev_node *dev_p = 0;
if (!owr_devl->devices)
return -1;
// get all base addresses
owr = (owr_t **) memmgr_alloc(sizeof(owr)*owr_devl->size);
//dbg_print("> owr size: %d\n", owr_devl->size);
for (i = 0, dev_p = owr_devl->devices; i < owr_devl->size;
++i, dev_p = dev_p->next) {
owr[i] = (owr_t *) dev_p->base;
// Default configuration
owr[i]->CDR = (OWR_CDR_NOR(DEFAULT_OWR_DIVIDER_NOR)) |
(OWR_CDR_OVD(DEFAULT_OWR_DIVIDER_OVD));
//dbg_print("> owr addr[%d]: %08X\n", i, owr[i]);
}
//owr = (owr_t *)owr_devl->devices->base;
return 0;
int i;
struct dev_node *dev_p = 0;
if (!owr_devl->devices)
return -1;
// get all base addresses
owr = (owr_t **) memmgr_alloc(sizeof(owr)*owr_devl->size);
//dbg_print("> owr size: %d\n", owr_devl->size);
for (i = 0, dev_p = owr_devl->devices; i < owr_devl->size;
++i, dev_p = dev_p->next) {
owr[i] = (owr_t *) dev_p->base;
// Default configuration
owr[i]->CDR = (OWR_CDR_NOR(DEFAULT_OWR_DIVIDER_NOR)) |
(OWR_CDR_OVD(DEFAULT_OWR_DIVIDER_OVD));
dbg_print("> owr addr[%d]: %08X\n", i, owr[i]);
}
dbg_print("> owr size: %d\n", owr_devl->size);
//owr = (owr_t *)owr_devl->devices->base;
return 0;
}
void owr_exit(void)
{
memmgr_free(owr);
memmgr_free(owr);
}
int oc_owr_poll(unsigned int id)
{
return (owr[id]->CSR & OWR_CSR_CYC) ? 1 : 0;
return (owr[id]->CSR & OWR_CSR_CYC) ? 1 : 0;
}
int oc_owr_reset(unsigned int id, int port)
{
// Request reset
owr[id]->CSR = OWR_CSR_SEL(port) | OWR_CSR_CYC | OWR_CSR_RST;
// Request reset
owr[id]->CSR = OWR_CSR_SEL(port) | OWR_CSR_CYC | OWR_CSR_RST;
// Wait for completion
while(oc_owr_poll(id));
// Wait for completion
while(oc_owr_poll(id));
// Read presence status. 0 -> presence detected, 1 -> presence NOT detected
//return (owr[id]->CSR & OWR_CSR_DAT) ? 0 : 1;
return (~(owr[id]->CSR) & OWR_CSR_DAT);
// Read presence status. 0 -> presence detected, 1 -> presence NOT detected
//return (owr[id]->CSR & OWR_CSR_DAT) ? 0 : 1;
return (~(owr[id]->CSR) & OWR_CSR_DAT);
}
int oc_owr_slot(unsigned int id, int port, uint32_t in_bit, uint32_t *out_bit)
{
uint32_t rval;
uint32_t rval;
// Avoid breaking the code when just issuing a read command (out_bit can be null).
// This is the case when in_bit = 0 (write 0 slot), but not for in_bit = 1
// (write 1 and/or read slot)
if (!out_bit)
out_bit = &rval;
// Avoid breaking the code when just issuing a read command (out_bit can be null).
// This is the case when in_bit = 0 (write 0 slot), but not for in_bit = 1
// (write 1 and/or read slot)
if (!out_bit)
out_bit = &rval;
owr[id]->CSR = OWR_CSR_SEL(port) | OWR_CSR_CYC | (in_bit & OWR_CSR_DAT);
owr[id]->CSR = OWR_CSR_SEL(port) | OWR_CSR_CYC | (in_bit & OWR_CSR_DAT);
// Wait for completion
while(oc_owr_poll(id));
// Wait for completion
while(oc_owr_poll(id));
*out_bit = owr[id]->CSR & OWR_CSR_DAT;
*out_bit = owr[id]->CSR & OWR_CSR_DAT;
return 0;
return 0;
}
int oc_owr_read_bit(unsigned int id, int port, uint32_t *out_bit)
{
return oc_owr_slot(id, port, 0x1, out_bit);
return oc_owr_slot(id, port, 0x1, out_bit);
}
int oc_owr_write_bit(unsigned int id, int port, uint32_t in_bit, uint32_t *out_bit)
{
return oc_owr_slot(id, port, in_bit, out_bit);
return oc_owr_slot(id, port, in_bit, out_bit);
}
int read_byte(unsigned int id, int port, uint32_t *out_byte)
{
int i;
uint32_t owr_data = 0;
uint32_t owr_bit = 0;
int i;
uint32_t owr_data = 0;
uint32_t owr_bit = 0;
for (i = 0; i < 8; ++i) {
oc_owr_read_bit(id, port, &owr_bit);
owr_data |= owr_bit << i;
}
for (i = 0; i < 8; ++i) {
oc_owr_read_bit(id, port, &owr_bit);
owr_data |= owr_bit << i;
}
*out_byte = owr_data;
*out_byte = owr_data;
return 0;
return 0;
}
int write_byte(unsigned int id, int port, uint32_t in_byte)
{
int i;
uint32_t owr_data = 0;
uint32_t owr_byte = in_byte;
uint32_t owr_bit;
for (i = 0; i < 8; ++i) {
oc_owr_write_bit(id, port, owr_byte & 0x1, &owr_bit);
owr_data |= owr_bit << i;
owr_byte >> 1;
}
if(owr_data == in_byte)
return 0;
else
return -1;
int i;
uint32_t owr_data = 0;
uint32_t owr_byte = in_byte;
uint32_t owr_bit;
for (i = 0; i < 8; ++i) {
oc_owr_write_bit(id, port, owr_byte & 0x1, &owr_bit);
owr_data |= owr_bit << i;
owr_byte >>= 1;
}
if(owr_data == in_byte)
return 0;
else
return -1;
}
embedded-sw/dev/spi.c
View file @ 32d1b8ce
......@@ -6,6 +6,9 @@
#include "board.h" // Board definitions: SPI device structure
#include "spi.h" // SPI device functions
#include "memmgr.h" // malloc and free clones
#include "debug_print.h"
#define SPI_DELAY 50
// Global SPI handler.
spi_t **spi;
......@@ -23,15 +26,33 @@ int spi_init(void)
spi = (spi_t **) memmgr_alloc(sizeof(spi)*spi_devl->size);
spi_config = (uint32_t *) memmgr_alloc(sizeof(spi_config)*spi_devl->size);
//dbg_print("> spi size: %d\n", spi_devl->size);
dbg_print("> spi size: %d\n", spi_devl->size);
for (i = 0, dev_p = spi_devl->devices; i < spi_devl->size;
++i, dev_p = dev_p->next) {
spi[i] = (spi_t *) dev_p->base;
// Default configuration
spi[i]->DIVIDER = DEFAULT_SPI_DIVIDER & SPI_DIV_MASK;
spi[i]->CTRL = SPI_CTRL_ASS | SPI_CTRL_TXNEG;
//dbg_print("> spi addr[%d]: %08X\n", i, spi[i]);
spi_config[i] = SPI_CTRL_ASS | SPI_CTRL_TXNEG;
//spi[i]->CTRL = spi_config[i];
dbg_print("> spi addr[%d]: %08X\n", i, spi[i]);
dbg_print("> spi rx0 addr[%d]: %08X\n", i, &spi[i]->RX0);
dbg_print("> spi tx0 addr[%d]: %08X\n", i, &spi[i]->TX0);
dbg_print("> spi rx1 addr[%d]: %08X\n", i, &spi[i]->RX1);
dbg_print("> spi tx1 addr[%d]: %08X\n", i, &spi[i]->TX1);
dbg_print("> spi rx2 addr[%d]: %08X\n", i, &spi[i]->RX2);
dbg_print("> spi tx2 addr[%d]: %08X\n", i, &spi[i]->TX2);
dbg_print("> spi rx3 addr[%d]: %08X\n", i, &spi[i]->RX3);
dbg_print("> spi tx3 addr[%d]: %08X\n", i, &spi[i]->TX3);
dbg_print("> spi ctrl addr[%d]: %08X\n", i, &spi[i]->CTRL);
dbg_print("> spi divider addr[%d]: %08X\n", i, &spi[i]->DIVIDER);
dbg_print("> spi ss addr[%d]: %08X\n", i, &spi[i]->SS);
dbg_print("> reading some fields back:\n");
dbg_print("> spi ctrl_busy: %08X\n", spi[i]->CTRL & SPI_CTRL_GO_BSY);
dbg_print("> spi ctrl_ass: %08X\n", spi[i]->CTRL & SPI_CTRL_ASS);
dbg_print("> spi ctrl_txneg: %08X\n", spi[i]->CTRL & SPI_CTRL_TXNEG);
dbg_print("> spi ctrl_lsb: %08X\n", spi[i]->CTRL & SPI_CTRL_LSB);
dbg_print("> spi ctrl_dir: %08X\n", spi[i]->CTRL & SPI_CTRL_DIR);
}
//spi = (spi_t *)spi_devl->devices->base;;
return 0;
......@@ -77,6 +98,7 @@ void oc_spi_config(unsigned int id, int ass, int rx_neg, int tx_neg,
// For use only with spi three-wire mode
int oc_spi_three_mode_tx(unsigned int id, int ss, int nbits, uint32_t in)
{
dbg_print(">oc_spi_three_mode_tx...\n");
// Write configuration to SPI core. SPI_CTRL_DIR = 1
spi[id]->CTRL = spi_config[id] | SPI_CTRL_DIR | SPI_CTRL_CHAR_LEN(nbits);
......@@ -89,7 +111,9 @@ int oc_spi_three_mode_tx(unsigned int id, int ss, int nbits, uint32_t in)
spi[id]->CTRL |= SPI_CTRL_GO_BSY;
// Wait for completion
while(oc_spi_poll(id));
dbg_print(">oc_spi_three_mode_tx: waiting to spi...\n");
while(oc_spi_poll(id))
delay(SPI_DELAY);
return 0;
}
......@@ -97,6 +121,7 @@ int oc_spi_three_mode_tx(unsigned int id, int ss, int nbits, uint32_t in)
// For use only with spi three-wire mode
int oc_spi_three_mode_rx(unsigned int id, int ss, int nbits, uint32_t *out)
{
dbg_print(">oc_spi_three_mode_rx...\n");
// Write configuration to SPI core. SPI_CTRL_DIR = 0
spi[id]->CTRL = spi_config[id] | SPI_CTRL_CHAR_LEN(nbits);
spi[id]->SS = (1 << ss);
......@@ -105,17 +130,20 @@ int oc_spi_three_mode_rx(unsigned int id, int ss, int nbits, uint32_t *out)
spi[id]->CTRL |= SPI_CTRL_GO_BSY;
// Wait for reception
while(oc_spi_poll(id));
dbg_print(">oc_spi_three_mode_rx: waiting to spi...\n");
while(oc_spi_poll(id))
delay(SPI_DELAY);
*out = spi[id]->RX0;
return 0;
}
int oc_spi_txrx(unsigned int id, int ss, int nbits, int write, uint32_t in, uint32_t *out)
int oc_spi_txrx(unsigned int id, int ss, int nbits, uint32_t in, uint32_t *out)
{
uint32_t rval;
dbg_print(">oc_spi_txrx...\n");
// Avoid breaking the code when just issuing a read command (out can be null)
if (!out)
out = &rval;
......@@ -130,7 +158,9 @@ int oc_spi_txrx(unsigned int id, int ss, int nbits, int write, uint32_t in, uint
spi[id]->SS = (1 << ss);
spi[id]->CTRL |= SPI_CTRL_GO_BSY;
while(oc_spi_poll(id));
dbg_print(">oc_spi_txrx: waiting to spi...\n");
while(oc_spi_poll(id))
delay(SPI_DELAY);
*out = spi[id]->RX0;
......
embedded-sw/dev/uart.c
View file @ 32d1b8ce
......@@ -2,56 +2,66 @@
#include "board.h" // Board definitions: UART device structure
#include "uart.h" // UART device functions
#include "debug_print.h"
#include "memmgr.h"
#define CALC_BAUD(baudrate) \
( ((( (unsigned long long)baudrate * 8ULL) << (16 - 7)) + \
(CPU_CLOCK >> 8)) / (CPU_CLOCK >> 7) )
( ((( (unsigned long long)baudrate * 8ULL) << (16 - 7)) + \
(CPU_CLOCK >> 8)) / (CPU_CLOCK >> 7) )
// Global UART handler.
uart_t **uart;
int uart_init(void)
{
int i;
struct dev_node *dev_p = 0;
int i;
struct dev_node *dev_p = 0;
if (!uart_devl->devices)
return -1;
if (!uart_devl->devices)
return -1;
// get all base addresses
uart = (uart_t **) memmgr_alloc(sizeof(uart_t *)*uart_devl->size);
// get all base addresses
uart = (uart_t **) memmgr_alloc(sizeof(uart_t *)*uart_devl->size);
//dbg_print("> uart size: %d\n", uart_devl->size);
for (i = 0, dev_p = uart_devl->devices; i < uart_devl->size;
++i, dev_p = dev_p->next) {
uart[i] = (uart_t *) dev_p->base;
uart[i]->BCR = CALC_BAUD(UART_BAUDRATE);
dbg_print("> uart addr[%d]: %08X\n", i, dev_p->base);
}
for (i = 0, dev_p = uart_devl->devices; i < uart_devl->size;
++i, dev_p = dev_p->next) {
uart[i] = (uart_t *) dev_p->base;
uart[i]->BCR = CALC_BAUD(UART_BAUDRATE);
//dbg_print("> uart addr[%d]: %08X\n", i, gpio[i]);
}
//uart = (uart_t *)uart_devl->devices->base;//BASE_GPIO;
return 0;
dbg_print("> uart size: %d\n", uart_devl->size);
//uart = (uart_t *)uart_devl->devices->base;//BASE_GPIO;
return 0;
}
int uart_exit()
{
// free uart structure
memmgr_free(uart);
return 0;
}
void uart_write_byte(unsigned int id, int b)
{
if (b == '\n')
uart_write_byte(id, '\r');
while (uart[id]->SR & UART_SR_TX_BUSY) ;
uart[id]->TDR = b;
if (b == '\n')
uart_write_byte(id, '\r');
while (uart[id]->SR & UART_SR_TX_BUSY) ;
uart[id]->TDR = b;
}
void uart_write_string(unsigned int id, char *s)
{
while (*s)
uart_write_byte(id, *(s++));
while (*s)
uart_write_byte(id, *(s++));
}
// Only for use with puts
void uart_default_write_string(char *s)
{
while (*s)
uart_write_byte(DEFAULT_UART, *(s++));
while (*s)
uart_write_byte(DEFAULT_UART, *(s++));
}
// See http://gcc.gnu.org/onlinedocs/gcc/Function-Attributes.html
......@@ -60,13 +70,13 @@ int puts(const char *s) __attribute__((alias("uart_default_write_string")));
int uart_poll(unsigned int id)
{
return uart[id]->SR & UART_SR_RX_RDY;
return uart[id]->SR & UART_SR_RX_RDY;
}
int uart_read_byte(unsigned int id)
{
if (!uart_poll(id))
return -1;
if (!uart_poll(id))
return -1;
return uart[id]->RDR & 0xff;
return uart[id]->RDR & 0xff;
}
embedded-sw/include/spi.h
View file @ 32d1b8ce
......@@ -16,13 +16,13 @@ typedef volatile struct SPI_WB spi_t;
int spi_init(void);
void spi_exit(void);
int oc_spi_poll(unsigned int id);
int oc_spi_three_mode(unsigned int id);
void oc_spi_config(unsigned int id, int ass, int rx_neg, int tx_neg,
int lsb, int ie);
// For use only with spi three-wire mode
int oc_spi_three_mode_tx(unsigned int id, int ss, int nbits, uint32_t in)
int oc_spi_three_mode_tx(unsigned int id, int ss, int nbits, uint32_t in);
// For use only with spi three-wire mode
int oc_spi_three_mode_rx(unsigned int id, int ss, int nbits, uint32_t *out)
int oc_spi_three_mode_rx(unsigned int id, int ss, int nbits, uint32_t *out);
int oc_spi_txrx(unsigned int id, int ss, int nbits, uint32_t in, uint32_t *out);
......
embedded-sw/include/uart.h
View file @ 32d1b8ce
......@@ -14,6 +14,7 @@ int mprintf(char const *format, ...);
/* UART API */
int uart_init(void);
int uart_exit(void);
void uart_write_byte(unsigned int id, int b);
void uart_write_string(unsigned int id, char *s);
int puts(const char *s);
......
embedded-sw/lib/debug_print.h
View file @ 32d1b8ce
......@@ -18,9 +18,9 @@ void debug_print2(const char *fmt, const char *data, int len);
#ifdef DEBUG_PRINT
#define dbg_print(fmt, ...) \
pp_printf("%s (%d): "fmt, __FILE__, __LINE__, ##__VA_ARGS__)
pp_printf("%s: %s (%d): "fmt, __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__)
#define dbg_print2(fmt, data, len) \
debug_print2(fmt, data, len)
debug_print2(fmt, data, len)
#else
#define dbg_print(...)
#define dbg_print2(fmt, data, len)
......
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