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Beam Positoning Monitor - Gateware
Commit 0d6cab67 authored by Lucas Russo's avatar Lucas Russo
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emb-sw/*fmc516*: add regular delay control support

parent 8ec6a363
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Showing with 2093 additions and 2034 deletions
embedded-sw/dbe.vhd
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embedded-sw/dbe_main.c
View file @ 0d6cab67
......@@ -448,17 +448,17 @@ void fmc516_test()
i, fmc516_isla216_get_chipver(i));
}
for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
pp_printf("> FMC516_ISLA216_ADC%d test mode off\n", i);
fmc516_isla216_write_byte(ISLA216_OUT_TESTMODE(ISLA216_OUT_TESTIO_OFF),
ISLA216_TESTIO_REG, i);
}
//for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
// fmc516_isla216_test_ramp(i);
// pp_printf("> FMC516_ISLA216_ADC%d: ramp test enabled!\n", i);
// pp_printf("> FMC516_ISLA216_ADC%d test mode off\n", i);
// fmc516_isla216_write_byte(ISLA216_OUT_TESTMODE(ISLA216_OUT_TESTIO_OFF),
// ISLA216_TESTIO_REG, i);
//}
for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
fmc516_isla216_test_ramp(i);
pp_printf("> FMC516_ISLA216_ADC%d: ramp test enabled!\n", i);
}
//for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
// fmc516_isla216_test_midscale(i);
// pp_printf("> FMC516_ISLA216_ADC%d: test miscale enabled!\n", i);
......
embedded-sw/fmc/fmc516/fmc516.c
View file @ 0d6cab67
......@@ -83,10 +83,10 @@ void fmc516_init_regs(unsigned int id)
fmc516_adj_delay(id, FMC516_ISLA216_ADC3, 5, 25, commit);
// Delay the falling edge of all channels
fmc516_fe_dly(id, FMC516_ISLA216_ADC0, 0, 0);
fmc516_fe_dly(id, FMC516_ISLA216_ADC1, 0, 0);
fmc516_fe_dly(id, FMC516_ISLA216_ADC2, 0, 0);
fmc516_fe_dly(id, FMC516_ISLA216_ADC3, 0, 0);
fmc516_fe_rg_dly(id, FMC516_ISLA216_ADC0, 0, 0, 0, 0);
fmc516_fe_rg_dly(id, FMC516_ISLA216_ADC1, 0, 0, 0, 0);
fmc516_fe_rg_dly(id, FMC516_ISLA216_ADC2, 0, 0, 0, 0);
fmc516_fe_rg_dly(id, FMC516_ISLA216_ADC3, 0, 0, 0, 0);
}
void fmc516_sweep_delays(unsigned int id)
......@@ -232,10 +232,11 @@ uint32_t fmc516_read_adc3(unsigned int id)
}
// ADC delay falling edge control
void fmc516_fe_dly(unsigned int id, int ch, int fe_dly_d1, int fe_dly_d2)
void fmc516_fe_rg_dly(unsigned int id, int ch, int fe_dly_d1, int fe_dly_d2,
int rg_dly_d1, int rg_dly_d2)
{
uint32_t *fmc_ch_handler;
uint32_t fe_dly_reg;
uint32_t dly_ctl_reg;
switch(ch) {
case FMC516_ISLA216_ADC0:
......@@ -256,15 +257,24 @@ void fmc516_fe_dly(unsigned int id, int ch, int fe_dly_d1, int fe_dly_d2)
}
// Read register value once
fe_dly_reg = *fmc_ch_handler;
dly_ctl_reg = *fmc_ch_handler;
if (fe_dly_d2)
fe_dly_reg |= (fe_dly_reg & ~FMC516_CH0_DLY_CTL_FE_DLY_MASK) |
dly_ctl_reg |= (dly_ctl_reg & ~FMC516_CH0_DLY_CTL_FE_DLY_MASK) |
FMC516_CH0_DLY_CTL_FE_DLY_W(0x3);
else if (fe_dly_d1)
fe_dly_reg |= (fe_dly_reg & ~FMC516_CH0_DLY_CTL_FE_DLY_MASK) |
dly_ctl_reg |= (dly_ctl_reg & ~FMC516_CH0_DLY_CTL_FE_DLY_MASK) |
FMC516_CH0_DLY_CTL_FE_DLY_W(0x1);
if (rg_dly_d2)
dly_ctl_reg |= (dly_ctl_reg & ~FMC516_CH0_DLY_CTL_RG_DLY_MASK) |
FMC516_CH0_DLY_CTL_RG_DLY_W(0x3);
else if (rg_dly_d1)
dly_ctl_reg |= (dly_ctl_reg & ~FMC516_CH0_DLY_CTL_RG_DLY_MASK) |
FMC516_CH0_DLY_CTL_RG_DLY_W(0x1);
// Write register value once
*fmc_ch_handler = fe_dly_reg;
*fmc_ch_handler = dly_ctl_reg;
dbg_print("dly_ctl_reg, *fmc_ch_handler = %08X, %08X\n", dly_ctl_reg, *fmc_ch_handler);
}
embedded-sw/include/fmc/fmc516/fmc516.h
View file @ 0d6cab67
......@@ -42,5 +42,6 @@ uint32_t fmc516_read_adc1(unsigned int id);
uint32_t fmc516_read_adc2(unsigned int id);
uint32_t fmc516_read_adc3(unsigned int id);
void fmc516_fe_dly(unsigned int id, int ch, int fe_dly_d1, int fe_dly_d2);
void fmc516_fe_rg_dly(unsigned int id, int ch, int fe_dly_d1, int fe_dly_d2,
int rg_dly_d1, int rg_dly_d2);
embedded-sw/include/hw/wb_fmc516.h
View file @ 0d6cab67
......@@ -3,7 +3,7 @@
* File : fmc516_regs.h
* Author : auto-generated by wbgen2 from wb_fmc516_regs.wb
* Created : Sat Mar 16 13:03:57 2013
* Created : Thu Mar 28 10:43:19 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc516_regs.wb
......@@ -213,10 +213,22 @@
#define FMC516_CH0_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 0 delay control register */
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Regular data delay in reg: Channel 0 delay control register */
#define FMC516_CH0_DLY_CTL_RG_DLY_MASK WBGEN2_GEN_MASK(8, 2)
#define FMC516_CH0_DLY_CTL_RG_DLY_SHIFT 8
#define FMC516_CH0_DLY_CTL_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 8, 2)
#define FMC516_CH0_DLY_CTL_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 8, 2)
/* definitions for field: Reserved in reg: Channel 0 delay control register */
#define FMC516_CH0_DLY_CTL_RESERVED_RG_DLY_MASK WBGEN2_GEN_MASK(10, 22)
#define FMC516_CH0_DLY_CTL_RESERVED_RG_DLY_SHIFT 10
#define FMC516_CH0_DLY_CTL_RESERVED_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 10, 22)
#define FMC516_CH0_DLY_CTL_RESERVED_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 10, 22)
/* definitions for register: Channel 1 status register */
......@@ -291,10 +303,22 @@
#define FMC516_CH1_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 1 delay control register */
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Regular data delay in reg: Channel 1 delay control register */
#define FMC516_CH1_DLY_CTL_RG_DLY_MASK WBGEN2_GEN_MASK(8, 2)
#define FMC516_CH1_DLY_CTL_RG_DLY_SHIFT 8
#define FMC516_CH1_DLY_CTL_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 8, 2)
#define FMC516_CH1_DLY_CTL_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 8, 2)
/* definitions for field: Reserved in reg: Channel 1 delay control register */
#define FMC516_CH1_DLY_CTL_RESERVED_RG_DLY_MASK WBGEN2_GEN_MASK(10, 22)
#define FMC516_CH1_DLY_CTL_RESERVED_RG_DLY_SHIFT 10
#define FMC516_CH1_DLY_CTL_RESERVED_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 10, 22)
#define FMC516_CH1_DLY_CTL_RESERVED_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 10, 22)
/* definitions for register: Channel 2 status register */
......@@ -369,10 +393,22 @@
#define FMC516_CH2_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 2 delay control register */
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Regular data delay in reg: Channel 2 delay control register */
#define FMC516_CH2_DLY_CTL_RG_DLY_MASK WBGEN2_GEN_MASK(8, 2)
#define FMC516_CH2_DLY_CTL_RG_DLY_SHIFT 8
#define FMC516_CH2_DLY_CTL_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 8, 2)
#define FMC516_CH2_DLY_CTL_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 8, 2)
/* definitions for field: Reserved in reg: Channel 2 delay control register */
#define FMC516_CH2_DLY_CTL_RESERVED_RG_DLY_MASK WBGEN2_GEN_MASK(10, 22)
#define FMC516_CH2_DLY_CTL_RESERVED_RG_DLY_SHIFT 10
#define FMC516_CH2_DLY_CTL_RESERVED_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 10, 22)
#define FMC516_CH2_DLY_CTL_RESERVED_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 10, 22)
/* definitions for register: Channel 3 status register */
......@@ -447,10 +483,22 @@
#define FMC516_CH3_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 3 delay control register */
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Regular data delay in reg: Channel 3 delay control register */
#define FMC516_CH3_DLY_CTL_RG_DLY_MASK WBGEN2_GEN_MASK(8, 2)
#define FMC516_CH3_DLY_CTL_RG_DLY_SHIFT 8
#define FMC516_CH3_DLY_CTL_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 8, 2)
#define FMC516_CH3_DLY_CTL_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 8, 2)
/* definitions for field: Reserved in reg: Channel 3 delay control register */
#define FMC516_CH3_DLY_CTL_RESERVED_RG_DLY_MASK WBGEN2_GEN_MASK(10, 22)
#define FMC516_CH3_DLY_CTL_RESERVED_RG_DLY_SHIFT 10
#define FMC516_CH3_DLY_CTL_RESERVED_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 10, 22)
#define FMC516_CH3_DLY_CTL_RESERVED_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 10, 22)
PACKED struct FMC516_WB {
/* [0x0]: REG Status register */
......
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