If we let the synthesis tool in its defauts attributes, the
pipeline gets removed and moved into a SRL primitive, causing
PCBs having ADC FMC data lines routed to oppositte FPGA I/O
banks to not meet timing. With these attributes we intruct
XST and MAP to keep the pipeline and not suck them into an
SRL, which would hurt the ability by MAP and PAR to move
the pipeline registers around to meet timing.