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Lucas Russo authored
For Artix7 with VAR_LOAD mode, the CE pin must be tied to low, in order to not increment or decrement the idelay value at each clock cycle (7 Series FPGAs SelectIO Resources User Guide, page 120)
ede3e544
For Artix7 with VAR_LOAD mode, the CE pin must be tied to low, in order to not increment or decrement the idelay value at each clock cycle (7 Series FPGAs SelectIO Resources User Guide, page 120)