Skip to content
GitLab
Explore
Sign in
Projects
Beam Positoning Monitor - Gateware
Repository
bpm-gw
hdl
modules
dbe_wishbone
wb_acq_core
wbgen
build_wb.sh
Find file
Blame
History
Permalink
hdl/modules/*/wb_acq_core/wbgen/*: remove ext_clk_i sync clock
· 1df7b7f4
Lucas Russo
authored
Nov 19, 2013
This was causing timing errors as ext_clk_i is 2x the clk_sys
1df7b7f4