BabyWR
Project description
BabyWR is being developed as a cost effective and small pluggable WR node. BabyWR has a M.2 form-factor. BabyWR is designed for low phase noise (10 MHz; -105 dBc/Hz @ 10 Hz) timing generation. For applications that demand ultimate low phase noise, an external high precision oscillator can be disciplined and used as reference clock.
BabyWR-Carrier is a SPEC like PCIe card (Figure 2) that can accept a BabyWR for test purposes. Like the SPEC, BabyWR-Carrier has a PCIe interface, an SFP+ cage, a (not fully populated) LPC FMC connector, JTAG- and USB-interface, LEDs, button and GPIO headers.
BabyWR Main Features
Figure 1: Preliminary 3D view of the BabyWR PCB.
BabyWR Main Features
- M.2 Type 22 60-D6-M
- Form-factor 22x60 mm
- Key-M (Socket 3 PCIe-based Adapter)
- PCIe x1 Gen3
-
Xilinx Artix UltraScale+ xcau10p-sbvb484-1 or xcau15p-sbvb484-1 (-1= slowest, commercial temp range, fast enough for most applications)
- 12 GTH (12.5 Gb/s: 1 used for PCIe, 1 used for SFP)
- 2 GTH reference clocks (PCIe clock, Local WR refclk, External WR refclk via M.2 connector, External WR refclk via W.FL coax or M.2 connector)
- Clocking resources
- 1x SiTime5359-125.000 MHz DCTCXO WR local reference clock (-85 dBc/Hz @ 10 Hz)
- 1x SiTime5359-124.992 MHz DCTCXO WR dmtd helper clock (-85 dBc/Hz @ 10 Hz)
- Possibility for connecting high precision low phase noise external reference oscillator via either M.2 connector (pin 17, 19) or via W.FL connectors (3, 4)
- On board memory
- 128 Mbit FLASH (can contain 2 FPGA configuration images)
- 64K (8K x 8-bit) I2C Serial EEPROM (24AA64T-I/MC) for storing serial number, calibration parameters and other critical data
- 2K (128 x 8-bit) I2C Serial EEPROM (24AA025E48) which provides EUI-48
- Miscellaneous
- 4x W.FL coaxial conectors (1-2 for absolute calibration or general purpose, 3-4 for external reference clock)
- JTAG interface via M.2 connector pins
- SFP logical signals (I2C, LOS_Fault, Mod_ABS) via M.2 connector pins
- 10 MHz, 1 PPS differential outputs via M.2 connector pins
- 9 GPIO3V3 lines (can be used for: UART, SPI DAC interface for external reference oscillator, reset, auxiliary I2C, etc.)
- 3 GPIO1V8 lines (can be used for: reset etc.)
- 10 MHz, 1 PPS differential inputs on testpads (possibility to use BabyWR in Grand-Master mode)
- 4 GPIO LEDs
- 1 LED FPGA configuration DONE
- SMD 0402 land pattern used as configuration button.
- 8 layer PCB
- All signals ESD protected
- Power consumption
- 3V3 estimated 1,8 Watt
BabyWR-Carrier
Figure 2: Preliminary 3D view of the BabyWR-Carrier PCB.
BabyWR-Carrier Main Features
- PCIe x1 Gen3 Carrier Board
- a test vehicle for BabyWR M.2 module
- FMC slot with LPC connector containing IO signals from BabyWR
- 7 differential pairs
- 5 single ended signals
- Vadj 3V3
- Front panel containing
- 1x Small Formfactor Pluggable+ (SFP+) cage for fibre-optic transceiver (WhiteRabbit support)
- Red and Green LEDs connected to programmable BabyWR GPIO lines
- Internal connectors
- M.2 Card Connector, Key-M, Height 4.2
- 1x JTAG header to access BabyWR Xilinx programming and during debugging
- 1x USB-C connector
- Can serve two UARTs over the same single USB-C connector with CP2105 - Dual UART bridge IC
- UART signals available on programmable BabyWR GPIO signals
- 10x SMA connectors
- 2x for differential external 125 MHz WR reference clock input from optional high precision external oscillator
- 2x for differential 10 MHz output clock (or other signal depending on BabyWR configuration)
- 2x for differential PPS output (or other signal depending on BabyWR configuration)
- 4x SMA connectors that translate to 4x W.FL connectors
- 4x W.FL connectors that can connected the BabyWR W.FL connectors via coax
- access to BabyWR optional external reference clock and RF GPIO (W.FL connectors)
- 1x10 pin header for access programmable BabyWR 3V3 GPIO signals
- 1x5 pin header for access programmable BabyWR 1V8 GPIO signals
- 4x 3-pin jumper to select UART or FMC pins for connecting to programmable BabyWR GPIO signals
- 2 Test points for BabyWR power Supply current sensing (20mV/A)
- Stand-alone features
- External 12V ATX power supply connector
- USB-C connector
- SFP+ cage for fibre-optic transceiver (WhiteRabbit support)
- 4x LEDs on programmable BabyWR GPIO lines
- 1x Button on programmable BabyWR GPIO line (e.g. for Reset)
- All signals ESD protected
- 8 layer PCB
- Power consumption estimated 2-3 W
Project information
- Official production documentation
- BabyWR Schematics (Note: Design created with Mentor Graphics using a Xpedition License).
- BabyWR Manufacturing files (Note: PCB Design created with Mentor Graphics using a Xpedition License)
- BabyWR-Carrier Schematics (Note: Design created with Mentor Graphics using a Xpedition License).
- BabyWR-Carrier Manufacturing files (Note: PCB Design created with Mentor Graphics using a Xpedition License)
- Frequently Asked Questions
- VCXOPlayGround_i2c, a pre-study project was started to test the feasibility of SiTime-5359 I2C controllable DCTCXO
- Related BabyWR information
Projects that are planning to use BabyWR
Contacts
Commercial producers
- Once designed and debugged, the board might become commercially available.
General questions about project
- Peter Jansweijer, Guido Visser - Nikhef
Status
Date | Event |
---|---|
03-01-2022 | Start working on project. |
05-07-2022 | BabyWR PCB layout Ready, BabyWR-Carrier PCB layout starting. |
13-09-2022 | BabyWR PCB layout revised, BabyWR-Carrier PCB layout ready. |
21-11-2022 | 5 BabyWR-Carrier boards received. |
21 November 2022