BabyWR V2.0
- Issues that led to a next version:
Figure 2: BabyWR Phase Noise performance.
Figure 2 shows the 10MHz Phase Noise performance of BabyWR (blue trace). The orange trace shows the performance of the SiTime reference oscillator (in this case 100MHz). In order to be able to compare the 10 and 100 MHz trace the SiTime 100 MHz trace is normalized to 10MHz by subtracting 20 dB (this is just an indication; in reality the dashed line may be below the actual noise floor at higher offset frequencies).
It can be seen that from ~30 Hz and beyond the noise floor is dominated by the FPGA.
BabyWR Main Features
- M.2 Type 2260-D6-M
- Form-factor 22x60 mm
- Key-M (Socket 3 PCIe-based Adapter)
- PCIe x1 Gen3
-
Xilinx Artix UltraScale+ xcau10p-sbvb484-1 (-1= slowest, commercial temp range, fast enough for most applications). Note that xcau15p-sbvb484-1 is pin compatible.
- 12 GTH (12.5 Gb/s: 1 used for PCIe, 1 used for SFP)
- 2 GTH reference clocks (PCIe clock, Local WR refclk, External WR refclk via M.2 connector, External WR refclk via U.FL coax or M.2 connector)
- Clocking resources
- 1x SiTime5359-100.000 MHz (or 125.000 MHz) DCTCXO WR local reference clock (-85 dBc/Hz @ 10 Hz)
- 1x SiTime5359-124.992 MHz DCTCXO WR dmtd helper clock (-85 dBc/Hz @ 10 Hz)
- Possibility for connecting high precision low phase noise external reference oscillator via either M.2 connector (pin 17, 19) or via U.FL connectors (2, 3)
- On board memory
- 128 Mbit FLASH (can contain 2 FPGA configuration images)
- 64K (8K x 8-bit) I2C Serial EEPROM (24AA64T-I/MC) for storing serial number, calibration parameters and other critical data
- 2K (128 x 8-bit) I2C Serial EEPROM (24AA025E48) which provides EUI-48
- Miscellaneous
- 4x W.FL coaxial connectors (1-2 for absolute calibration or general purpose, 3-4 for external reference clock)
- JTAG interface via M.2 connector pins
- SFP logical signals (I2C, LOS_Fault, Mod_ABS) via M.2 connector pins
- WRCLK (default 10 MHz), 1 PPS differential outputs via M.2 connector pins
- 9 GPIO3V3 lines (can be used for: UART, SPI DAC interface for external reference oscillator, reset, auxiliary I2C, etc.)
- 3 GPIO1V8 lines (can be used for: reset etc.)
- 10 MHz, 1 PPS differential inputs on testpads (possibility to use BabyWR in Grand-Master mode)
- 4 GPIO LEDs
- 1 LED FPGA configuration DONE
- SMD 0402 land pattern used as configuration button.
- 8 layer PCB
- All signals ESD protected
- Power consumption
- 1,6 Watt (3V3)
Project information
- Official production documentation
- BabyWR Schematics 11300.09.02.1 (Note: Design created with Mentor Graphics using a Xpedition License).
- BabyWR Manufacturing files 11300.09.02.1 (Note: PCB Design created with Mentor Graphics using a Xpedition License)
- Phase Noise performance
- Although the first prototype BabyWR is fully functional the Phase Noise performance does not meet expectations. Currently a design study is ongoing to mitigate this issue. The next iteration of BabyWR will probably have a 22x80 mm M.2 form-factor (instead of 22x60 mm)
- Read more about Artix Ultrascale+ Phase Noise performance measurements.
Serial numbers
|----+---------+----------------------------|
| Sn | FPGA | Remark |
|----+---------+----------------------------|
| 1 | XCAU10P | Broken |
| 2 | XCAU10P | |
| 3 | XCAU15P | |
| 4 | XCAU15P | |
| 5 | XCAU15P | X1 = 100 MHz |
| 6 | XCAU15P | No Oscillators mounted yet |
|----+---------+----------------------------|
Contacts
General questions about project
- Peter Jansweijer, Guido Visser - Nikhef
Status
Date | Event |
---|---|
07-11-2023 | Moved old BabyWR V2.0 information to this page. |
22 April 2024