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**BabyWR** is being developed as a cost effective and small pluggable WR node. BabyWR has a [M.2 form-factor](https://en.wikipedia.org/wiki/M.2). BabyWR is designed for low phase noise (10 MHz; -105 dBc/Hz @ 10 Hz) timing generation. For applications that demand ultimate low phase noise, an external high precision oscillator can be disciplined and used as reference clock.
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**BabyWR-Carrier** is a [SPEC](https://ohwr.org/project/spec/wikis/home) like PCIe card ([Figure 2](#babywr-carrier)) that can accept a BabyWR for test purposes. Like the SPEC, BabyWR-Carrier has a PCIe interface, an SFP+ cage, a (not fully populated) LPC FMC connector, JTAG- and USB-interface, LEDs, button and GPIO headers.
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**BabyWR-Carrier** is a [SPEC](https://ohwr.org/project/spec/wikis/home) like PCIe card ([Figure 3](#babywr-carrier)) that can accept a BabyWR for test purposes. Like the SPEC, BabyWR-Carrier has a PCIe interface, an SFP+ cage, a (not fully populated) LPC FMC connector, JTAG- and USB-interface, LEDs, button and GPIO headers.
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## BabyWR Main Features
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![BabyWR_v2_0](uploads/b98adba1124e8d9601472ea6fda65250/BabyWR_v2_0.jpg)
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![BabyWR_v2_0](uploads/b98adba1124e8d9601472ea6fda65250/BabyWR_v2_0.jpg)
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_Figure 1: BabyWR PCB._
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![BabyWR_v2_0](uploads/d0fe9032509647924348595bb1ec441e/BabyWR_Sn5_10MHz_gs2kp600ki2_sit5359_100MHz.png)
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_Figure 2: BabyWR Phase Noise performance._
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Figure 2 shows the 10MHz Phase Noise performance of BabyWR (blue trace). The orange trace shows the performance of the SiTime reference oscillator (in this case 100MHz). In order to be able to compare the 10 and 100 MHz trace the SiTime 100 MHz trace is normalized to 10MHz by subtracting 20 dB (this is just an indication; in reality the dashed line may be below the actual noise floor at higher offset frequencies).
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It can be seen that from ~30 Hz and beyond the noise floor is dominated by the FPGA.
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## BabyWR Main Features
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- M.2 Type 22 60-D6-M
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- Form-factor 22x60 mm
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- 12 GTH (12.5 Gb/s: 1 used for PCIe, 1 used for SFP)
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- 2 GTH reference clocks (PCIe clock, Local WR refclk, External WR refclk via M.2 connector, External WR refclk via U.FL coax or M.2 connector)
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- Clocking resources
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- 1x [SiTime5359](https://www.sitime.com/products/super-tcxos/sit5359)-125.000 MHz DCTCXO WR local reference clock (-85 dBc/Hz @ 10 Hz)
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- 1x [SiTime5359](https://www.sitime.com/products/super-tcxos/sit5359)-125.000 (or 100.000) MHz DCTCXO WR local reference clock (-85 dBc/Hz @ 10 Hz)
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- 1x [SiTime5359](https://www.sitime.com/products/super-tcxos/sit5359)-124.992 MHz DCTCXO WR dmtd helper clock (-85 dBc/Hz @ 10 Hz)
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- Possibility for connecting high precision low phase noise external reference oscillator via either M.2 connector (pin 17, 19) or via U.FL connectors (3, 4)
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- On board memory
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## BabyWR-Carrier
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![BabyWR_Carrier](uploads/2d0a3f82e303ca6bb4ea8f96853a037b/_MG_8020-3.jpg)
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_Figure 2: BabyWR-Carrier PCB._
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_Figure 3: BabyWR-Carrier PCB._
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## BabyWR-Carrier Main Features
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- PCIe x1 Gen3 Carrier Board
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- a test vehicle for BabyWR M.2 module
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| 05-04-2023 | 4 more BabyWR M.2 modules boards received or further testing and characterization. |
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| 03-11-2023 | Layout for a next version BabyWR M.2 module is in progress.|
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| 07-11-2023 | Four BabyWR Carriers (next version repairing few bugs) received and functional.
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| 11-03-2024 | Received 5 BabyWR_2280-D6-M boards (with ReClocking FlipFlops; unfortunately the wrong PCB thickness).
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| 13-03-2024 | Added Phase Noise performance for BabyWR v2.0.
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-----
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26 February 2024 |
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\ No newline at end of file |
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13 March 2024 |
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\ No newline at end of file |