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## Project description
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**BabyWR** is being developed as a cost effective and small pluggable WR node. BabyWR has a [M.2 form-factor](https://en.wikipedia.org/wiki/M.2). BabyWR is designed for low phase noise (10 MHz; < -100 dBc/Hz @ 10 Hz) timing generation. For applications that demand ultimate low phase noise, an external high precision oscillator can be disciplined and used as reference clock.
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**BabyWR** is being developed as a cost effective and small pluggable WR node. BabyWR has a [M.2 form-factor](https://en.wikipedia.org/wiki/M.2). BabyWR is designed for low phase noise (10 MHz; < -100 dBc/Hz @ 10 Hz) timing generation. For applications that demand ultimate low phase noise, an external high precision oscillator can be disciplined and used as reference clock.
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This M.2 Type 2280-D6-M form factor module is a Phase Noise improved version of [it's predecessor](https://ohwr.org/project/babywr/wikis/BabyWR-carrier_V2.0). The 10 MHz and 1 PPS signals that are generated by the [White Rabbit PTP Core](https://ohwr.org/project/wr-cores/wikis/Wrpc-core) on the FPGA are re-clocked by the clean reference oscillator. By re-arranging the assembly of a few resistors, the module allows to output the clean 100 MHz reference clock signal directly, once "lock sweep" is implemented.
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**BabyWR-Carrier** is a [SPEC](https://ohwr.org/project/spec/wikis/home) like PCIe card ([Figure 3](#babywr-carrier)) that can accept a BabyWR for test purposes. Like the SPEC, BabyWR-Carrier has a PCIe interface, an SFP+ cage, a (not fully populated) LPC FMC connector, JTAG- and USB-interface, LEDs, button and GPIO headers.
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## BabyWR Main Features
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![BabyWR_v2_0](uploads/b98adba1124e8d9601472ea6fda65250/BabyWR_v2_0.jpg)
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_Figure 1: BabyWR PCB (11300.09.01.1)._
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![BabyWR_2280-D6-M_v1.0_FrontEuro](uploads/f0fa3f5efa731efb6505c2f0610a97d7/BabyWR_2280-D6-M_v1.0_FrontEuro.jpg)
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_Figure 1: BabyWR PCB (11300.13.01.1)._
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![BabyWR_v2_0](uploads/d0fe9032509647924348595bb1ec441e/BabyWR_Sn5_10MHz_gs2kp600ki2_sit5359_100MHz.png)
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![BabyWR_2280_D6_M_10MHz](uploads/e5c54230fb91e3f6962b08fc5f330a97/BabyWR_2280_D6_M_10MHz.png)
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_Figure 2: BabyWR Phase Noise performance._
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Figure 2 shows the 10MHz Phase Noise performance of BabyWR (blue trace). The orange trace shows the performance of the SiTime reference oscillator (in this case 100MHz). In order to be able to compare the 10 and 100 MHz trace the SiTime 100 MHz trace is normalized to 10MHz by subtracting 20 dB (this is just an indication; in reality the dashed line may be below the actual noise floor at higher offset frequencies).
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It can be seen that from ~30 Hz and beyond the noise floor is dominated by the FPGA.
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From 1 KHz and beyond the noise floor is dominated by the re-clocking Flip-Flops.
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## BabyWR Main Features
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- M.2 Type 22 60-D6-M
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- Form-factor 22x60 mm
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- M.2 Type 2280-D6-M
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- Form-factor 22x80 mm
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- Key-M (Socket 3 PCIe-based Adapter)
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- PCIe x1 Gen3
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- [Xilinx Artix UltraScale+](https://www.xilinx.com/content/dam/xilinx/publications/product-briefs/xilinx-artix-ultrascale-plus-product-brief.pdf) xcau10p-sbvb484-1 (-1= slowest, commercial temp range, fast enough for most applications). Note that xcau15p-sbvb484-1 is pin compatible.
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- 12 GTH (12.5 Gb/s: 1 used for PCIe, 1 used for SFP)
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- 2 GTH reference clocks (PCIe clock, Local WR refclk, External WR refclk via M.2 connector, External WR refclk via U.FL coax or M.2 connector)
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- Clocking resources
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- 1x [SiTime5359](https://www.sitime.com/products/super-tcxos/sit5359)-125.000 (or 100.000) MHz DCTCXO WR local reference clock (-85 dBc/Hz @ 10 Hz)
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- 1x [SiTime5359](https://www.sitime.com/products/super-tcxos/sit5359)-100.000 MHz DCTCXO WR local reference clock (-85 dBc/Hz @ 10 Hz)
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- 1x [SiTime5359](https://www.sitime.com/products/super-tcxos/sit5359)-124.992 MHz DCTCXO WR dmtd helper clock (-85 dBc/Hz @ 10 Hz)
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- Possibility for connecting high precision low phase noise external reference oscillator via either M.2 connector (pin 17, 19) or via U.FL connectors (2, 3)
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- 1:4 clock fan-out and two re-clocking Flip-Flops to cleanup 10 MHz and 1 PPS
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- On board memory
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- 128 Mbit FLASH (can contain 2 FPGA configuration images)
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- 64K (8K x 8-bit) I2C Serial EEPROM (24AA64T-I/MC) for storing serial number, calibration parameters and other critical data
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## Project information
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- Official production documentation
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- [BabyWR Schematics 11300.09.02.1](uploads/d3dd3b14852122ba2c5e8ba4596368dd/11300.09.02.1_SCH.PDF) (Note: Design created with Mentor Graphics using a Xpedition License).
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- [BabyWR Manufacturing files 11300.09.02.1](uploads/069672cac79fbf2d7d9d8ce451c08f9b/11300.09.02.1_PCB.ZIP) (Note: PCB Design created with Mentor Graphics using a Xpedition License)
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- [BabyWR Schematics 11300.13.02.1](uploads/64d0d92652132f5607ecb9104a673ba9/11300.13.02.1_SCH.PDF) (Note: Design created with Mentor Graphics using a Xpedition License).
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- BabyWR PCB Manufacturing files 11300.13.01.1_PCB (available once [Qualified by the WR Calaboration](https://www.white-rabbit.tech/tests/)) (Note: PCB Design created with Mentor Graphics using a Xpedition License)
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- BabyWR Assembly Manufacturing files 11300.13.01.1_PCA (available once [Qualified by the WR Calaboration](https://www.white-rabbit.tech/tests/)) (Note: PCB Design created with Mentor Graphics using a Xpedition License)
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- [BabyWR-Carrier Schematics 11300.10.02.1](uploads/74d9b05c821e945153158e17f3ecc57f/11300.10.02.2_SCH_CleanedUp.pdf) (Note: Design created with Mentor Graphics using a Xpedition License).
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- [BabyWR-Carrier Manufacturing files 11300.10.02.1](uploads/99e9314b92f37264cc9178ef14870545/11300.10.02.2_PCB_Variant-2280.ZIP) (Note: PCB Design created with Mentor Graphics using a Xpedition License)
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- [Frequently Asked Questions](/project/babywr/wikis/FAQ)
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... | ... | @@ -133,4 +136,4 @@ _Figure 3: BabyWR-Carrier PCB._ |
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-----
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15 March 2024 |
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25 March 2024 |
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