Micropipeline
Currently, only the basic micropipeline demo is available but this is a very good entry point to implementing asynchronous logic circuits in general and GALS in particular.
Ivan Sutherland introduced the term "micropipeline" in his 1988 Turing Award Lecture. Sutherland is widely regarded as the father of computer graphics. During his prolific career, he has received a plethora of honors and prizes. For the past few years, he has devoted himself to developing VLSI processing architectures, with a special emphasis on asynchronous logic.
To visualize the behavior of a micropipeline versus a standard clocked pipeline, we will use the metaphor of the bucket brigade -- a method for transporting items by passing them from one stationary person to the next. The bucket brigade resembles the structure of a static data pipeline, in which data is passed from one register to the next.
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A conventional synchronous pipeline is like a bucket brigade in which each member follows the beat of a clock. When the clock ticks, each person pushes a bucket forward. When the clock tocks, each person catches the bucket pushed by the preceding person.
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An asynchronous micropipeline behaves just as a real-world bucket brigade does. Each person who holds a bucket can pass it down the line as soon as the next person's hands are free. If there is no bucket available, the person waits for one.
Demo Description
The demo consist in a variable length FIFO that passes data through 32 bits registers. The first register implements a binary counter, so that a 32 bits count is generated and propagated to the last register in the FIFO.
In a synchronous pipeline, we would include all of the registers in a single clock domain. By using an asynchronous micropipeline approach, each of the 32 bits register will have its own local clock domain, acting as a trivial GALS design.
Associated to each stage of the asynchronous micropipeline, we will have a simple asynchronous rendezvous cell module that communicates with those associated to the neighboring stages to generate an ordered and interlocked sequence of clock pulses in each of the independent clock domains.
This are the three basic types of rendezvous modules used in the micropipeline demo:
- AsyncArt Source Rendezvous Cell: This is the rendezvous module associated to the first data register, that acts as the origin of the data. Without a previous stage, as soon as the next stage is ready it will fire its local clock and pass a new data to the micropipeline.
- AsyncArt Register Rendezvous Cell: This is the rendezvous module associated to the intermediate data registers. This will fire its local clock and load a new data when the previous stage has a new data available the next stage is empty.
- AsyncArt Sink Rendezvous Cell: This is the rendezvous module associated to the last data register, the one that exposes the data to the outside after crossing the micropipeline. Without a following stage, this will fire its local clock and load a new data in the output as soon as a it arrives from the previous stage.
In order to allow for an easier integration and testing in several devices, we provide the micropipeline demo in both VHDL and Verilog versions:
- https://www.ohwr.org/project/asyncart/blob/master/hdl/vhdl/asyncart_demo.vhd
- https://www.ohwr.org/project/asyncart/blob/master/hdl/verilog/asyncart_demo.v
Data Throughput
Depending on the depth of the pipeline, the pipeline performance will vary. This is because, when working at full speed, the complete micropipeline will be as fast as the slowest asynchronous handshaking stage.
Physical derives
By studying the micropipeline, you can check how fast your async design will be able to run and how physical derives have an impact in the speed of the CMOS circuitry, e.g.:
- The more the supply voltage is, the faster the circuit runs.
- The lower the die temperature is, the faster the circuit runs.