Reference Design Catalog
The original work conducted over FPGAs the AsyncArt project was targeted to Xilinx devices, specifically:
- Virtex-4 XC4VFX20: Xilinx ML405
- Spartan-3 XC3S200: Xilinx Spartan-3 Starter Kit
The collection of demo examples from the AsyncArt project was reviewed and migrated to Xilinx 6th Series devices and made publicly available in the date of 2012/12/29, so you will need the Xilinx ISE Webpack 14 Integrated Design Environment.
The AsyncArt project deriverables are then compressed full Xilinx ISE projects, all of them consisting in two fundamental blocks:
- TOP-Level Schematic: when dealing with asynchronous design, being conscious of the dynamics and geometry of critical signal paths is a key issue. By this reason, the AsyncArt reference designs are released as visually descriptive schematics files.
> Design tip: hierachy is critical when synthesizing an asynchronous design. For a successful synthesis, Keep Hierachy property should be enabled.
- HDL TestBench: as a quick-start to real work, with every schematic is attached a testbench ready to be simulated. This testbench contains information related to the input operation & purpose and the output that should be observed.
> Design tip: Real world delays are the big deal with asynchronous logic. For a successful simulation, Post Place & Route models should be used.
NOTE: A single design deliverable may contain more than one schematic/testbench pair
Library
The collection of schematics IP-Cores and associated symbols that comprises the library. By copying & editing the already available blocks, the library can be easily extended.
Micropipelines
Basic micropipelines structures inspired in the asynchronous logic research conducted by Ivan Sutherland. The main advantages of micropipelines are a power consuption that directly depends on data throughput, a very low logic overhead & an ultra fast performance.