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AMC FMC Carrier Kintex Ultrascale AFCKU
Commit c4299bc3 authored by Filip Świtakowski's avatar Filip Świtakowski
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v1.0 after review

parent 9985977a
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circuit_board/AFCKUv1.PrjPcbStructure → circuit_board/AFCKU.PrjPcbStructure
View file @ c4299bc3
......@@ -22,8 +22,8 @@ Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FHPC2|SchDesignator=FHP
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FMGT|SchDesignator=FMGT|FileName=FPGA_MGT.SchDoc|SheetNumber=13|SymbolType=Normal|RawFileName=FPGA_MGT.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FPGA_Supplies|SchDesignator=FPGA_Supplies|FileName=FPGA_Supplies.SchDoc|SheetNumber=15|SymbolType=Normal|RawFileName=FPGA_Supplies.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=FSDRAM|SchDesignator=FSDRAM|FileName=FPGA_SDRAM.SchDoc|SheetNumber=14|SymbolType=Normal|RawFileName=FPGA_SDRAM.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_10|SchDesignator=SUP_10|FileName=SUP_1V.SchDoc|SheetNumber=22|SymbolType=Normal|RawFileName=SUP_1V.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_18|SchDesignator=SUP_18|FileName=SUP_1.8_3.3.SchDoc|SheetNumber=20|SymbolType=Normal|RawFileName=SUP_1.8_3.3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_095|SchDesignator=SUP_095|FileName=SUP_VCCINT.SchDoc|SheetNumber=22|SymbolType=Normal|RawFileName=SUP_VCCINT.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_HPC18|SchDesignator=SUP_HPC18|FileName=SUP_1.8_FMC.SchDoc|SheetNumber=21|SymbolType=Normal|RawFileName=SUP_1.8_FMC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_HPC33|SchDesignator=SUP_HPC33|FileName=SUP_3.3_FMC.SchDoc|SheetNumber=23|SymbolType=Normal|RawFileName=SUP_3.3_FMC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=POWER_Management.SchDoc|Designator=SUP_linear|SchDesignator=SUP_linear|FileName=SUP_linear.SchDoc|SheetNumber=24|SymbolType=Normal|RawFileName=SUP_linear.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
......
circuit_board/AFCKU_panel.STEP 0 → 100644
View file @ c4299bc3
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circuit_board/CPU.Harness
View file @ c4299bc3
......@@ -5,5 +5,5 @@ I2C=SCL,SDA
JTAG=TRSTn,TMS,TDO,TDI,TCK
MISC=PRSNT,PG_M2C,PG_C2M
P_MON=FMC1_CRITICAL,FMC1_PV,FMC1_TC,FMC1_WARNING,FMC2_CRITICAL,FMC2_PV,FMC2_TC,FMC2_WARNING,AMC_RTM_CRITICAL,AMC_RTM_PV,AMC_RTM_TC,AMC_RTM_WARNING
PM_control=EN_RTM_MP,1V5_VTT_EN,EN_P1V8,EN_P1V5,EN_FMC1_P12V,EN_FMC2_P12V,EN_FMC1_P1V8,EN_FMC2_P1V8,EN_FMC1_P3V3,EN_FMC2_P3V3,EN_VCCINT,PGOOD_P1V0,EN_P3V3,EN_RTM_PWR
PM_control=EN_RTM_MP,1V5_VTT_EN,EN_P1V8,EN_P1V5,EN_FMC1_P12V,EN_FMC2_P12V,EN_FMC1_P1V8,EN_FMC2_P1V8,EN_FMC1_P3V3,EN_FMC2_P3V3,EN_VCCINT,PGOOD,EN_P3V3,EN_RTM_PWR
UART=TxD,RxD
circuit_board/CPU.SchDoc
View file @ c4299bc3
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circuit_board/Clock_management.Harness
View file @ c4299bc3
......@@ -2,7 +2,7 @@ AMC_FABRIC_CLOCK=FCLKA_P,FCLKA_N
AMC_TELECOM_CLOCK=TCLKA_N,TCLKA_P,TCLKB_N,TCLKB_P,TCLKC_N,TCLKC_P,TCLKD_N,TCLKD_P
FMC_CLOCKS=CLK0_M2C_N,CLK0_M2C_P,CLK1_M2C_N,CLK1_M2C_P,CLK2_BIDIR_N,CLK2_BIDIR_P,CLK3_BIDIR_N,CLK3_BIDIR_P,CLK_DIR
FPGA_CLK=FPGA_CLK_P,FPGA_CLK_N
FPGA_SDRAM_CLK=FPGA_CLK1_P,FPGA_CLK1_N,SI57X_SEC_CLK
FPGA_SDRAM_CLK=FPGA_CLK1_P,FPGA_CLK1_N,SEC_CLK_P,SEC_CLK_N
I2C=SDA,SCL
MGT_CLK=FCLK_GTP224_CLK0_P,FCLK_GTP224_CLK0_N,FLEX_GTP226_CLK1_P,FLEX_GTP226_CLK1_N,FLEX_GTP224_CLK1_P,FLEX_GTP224_CLK1_N,FLEX_GTP225_CLK1_P,FLEX_GTP225_CLK1_N,FLEX_GTP227_CLK1_P,FLEX_GTP227_CLK1_N,FLEX_GTP226_CLK0_P,FLEX_GTP226_CLK0_N,125_GTP225_CLK0_P,125_GTP225_CLK0_N
RTM_CLK=AMC_CLK_P,AMC_CLK_N,RTM_CLK_P,RTM_CLK_N,AMC_TCLK_P,AMC_TCLK_N,GTP0-3_CLK_OUT_P,GTP0-3_CLK_OUT_N,GTP4-7_CLK_OUT_P,GTP4-7_CLK_OUT_N
circuit_board/FPGA_SDRAM.Harness
View file @ c4299bc3
DDR3_x32=A[0..15],DQ[0..31],BA[0..2],CLK_P,CLK_N,R\A\S\,C\A\S\,C\S\,W\E\,ODT,CKE,R\E\S\E\T\,DQM[0..3],DQS_P[0..3],DQS_N[0..3]
FPGA_SDRAM_CLK=FPGA_CLK1_N,FPGA_CLK1_P,SI57X_SEC_CLK
I2C=SCL,SDA
FPGA_SDRAM_CLK=FPGA_CLK1_N,FPGA_CLK1_P,SEC_CLK_P,SEC_CLK_N
MLVDS-FPGA=MLVDS_O_1,MLVDS_O_2,MLVDS_O_3,MLVDS_O_4,MLVDS_O_5,MLVDS_O_6,MLVDS_O_7,MLVDS_O_8,MLVDS_I_1,MLVDS_I_2,MLVDS_I_3,MLVDS_I_4,MLVDS_I_5,MLVDS_I_6,MLVDS_I_7,MLVDS_I_8
circuit_board/POWER_Management.Harness
View file @ c4299bc3
FMC_J1_POWER=3P3VAUX,12P0V,VIO_B_M2C
PM_control=EN_RTM_MP,1V5_VTT_EN,EN_P1V8,EN_P1V5,EN_FMC1_P12V,EN_FMC2_P12V,EN_FMC1_P1V8,EN_FMC2_P1V8,EN_FMC1_P3V3,EN_FMC2_P3V3,EN_VCCINT,PGOOD_P1V0,EN_P3V3,EN_RTM_PWR
PM_control=EN_RTM_MP,1V5_VTT_EN,EN_P1V8,EN_P1V5,EN_FMC1_P12V,EN_FMC2_P12V,EN_FMC1_P1V8,EN_FMC2_P1V8,EN_FMC1_P3V3,EN_FMC2_P3V3,EN_VCCINT,PGOOD,EN_P3V3,EN_RTM_PWR
circuit_board/USB_SERIAL_QUAD.Harness
View file @ c4299bc3
UART=TxD,RxD
UART=RxD,TxD
USB_JTAG=USB_TDI,USB_TCK,USB_TMS,USB_TDO,USB_JTAG_ACTIVE,EN_USB_JTAG
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