Also, will we change from two memories to a single memory.
I note that having two memories is not the worse problem - switching
between them do work properly, and we have tested it at LNLS - but seems
unnecessary and complicated.
The main problem is having two bus masters (FPGA and MMC). I don't know
yet how to solve this elegantly.
I decided not to change the bus access. Some discipline on accessing the
bus should be enough to prevent conflicts in operation, and in the worst
case, the CPU can coordinate blocks.