Placement of PCIe core and corresponding MGTs is not optimal
According to Xilinx's recommendations, GTP 216 should be used as PCIe interface to ensure meeting timing requirements. However, in AFC v1 and v2 GTP 216 was connected to FP2 and GTP 113 was connected to FP1 (thus inverted), making timing closure difficult for Gen1 speed and impossible for Gen2 considering a -1 speed grade FPGA (explanation based on Adrian Byszuk's description).