FMC LA clock signals should be connected to MRCC not SRCC
FMC LA clock signals should be connected to MRCC (multi region clock) not SRCC while CLK_M2C and CLK_BIDIR should be connected to SRCC (single region clock)
CLK_M2C and CLK_BIDIR might be rerouted by ADN4604 to another bank if required. It is also possible to route SRCC internally to a global clock tree internally in FPGA.
In some cases (FMC112/FMC116) it would be useful to have FMC LA clock connected to clock input that can drive also another clock regions directly.