Commit acf5b6e9 authored by Henrique Silva's avatar Henrique Silva

Check clock switch Reset before configuring

There's a Reset IC in the AFC Board that only releases the clock switch
(ADN4604) reset pin only ~140ms after the P1v0GOOD signal goes high
parent d1f5fa95
......@@ -35,8 +35,16 @@ void adn4604_setup(void)
t_adn_connect_cfg cfg;
/* Disable UPDATE' pin by pulling it HIGH */
gpio_set_pin_dir(GPIO_ADN_UPDATE_PORT, GPIO_ADN_UPDATE_PIN, OUTPUT);
gpio_set_pin_state( GPIO_ADN_UPDATE_PORT, GPIO_ADN_UPDATE_PIN, HIGH);
/* There's a delay circuit in the Reset pin of the clock switch, we must wait until it clears out */
gpio_set_pin_dir( GPIO_ADN_RESETN_PORT, GPIO_ADN_RESETN_PIN, INPUT);
while( gpio_read_pin( GPIO_ADN_RESETN_PORT, GPIO_ADN_RESETN_PIN ) == 0) {
vTaskDelay(50);
}
if (i2c_take_by_busid(I2C_BUS_CPU_ID, &i2c_bus_id, (TickType_t)10) == pdFALSE) {
return;
}
......
......@@ -114,6 +114,8 @@
#define GPIO_ADN_UPDATE_PORT 1
#define GPIO_ADN_UPDATE_PIN 26
#define GPIO_ADN_RESETN_PORT 1
#define GPIO_ADN_RESETN_PIN 22
#endif
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment