Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
V
VME64x core - msaccani
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
1
Merge Requests
1
Wiki
Wiki
Snippets
Snippets
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Mathieu Saccani
VME64x core - msaccani
Commits
a994813b
Commit
a994813b
authored
Nov 11, 2019
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
vme64x_pkg: rename c_AM_A24_S to c_AM_A24
parent
b9f87fb9
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
9 additions
and
9 deletions
+9
-9
vme64x_pkg.vhd
hdl/rtl/vme64x_pkg.vhd
+2
-2
vme_bus.vhd
hdl/rtl/vme_bus.vhd
+1
-1
top_tb.vhd
hdl/testbench/simple_tb/top_tb.vhd
+6
-6
No files found.
hdl/rtl/vme64x_pkg.vhd
View file @
a994813b
...
...
@@ -79,8 +79,8 @@ package vme64x_pkg is
-- Table 2.4 "Extended Address Modifier Code" page 12 2eSST
-- ANSI/VITA 1.5-2003(R2009)
subtype
t_am_vec
is
std_logic_vector
(
5
downto
0
);
constant
c_AM_A24_S
_SUP
:
t_am_vec
:
=
"111101"
;
-- 0x3d
constant
c_AM_A24
_S
:
t_am_vec
:
=
"111001"
;
-- 0x39
constant
c_AM_A24_S
UP
:
t_am_vec
:
=
"111101"
;
-- 0x3d
constant
c_AM_A24
:
t_am_vec
:
=
"111001"
;
-- 0x39
constant
c_AM_A24_BLT
:
t_am_vec
:
=
"111011"
;
-- 0x3b
constant
c_AM_A24_BLT_SUP
:
t_am_vec
:
=
"111111"
;
-- 0x3f
constant
c_AM_A24_MBLT
:
t_am_vec
:
=
"111000"
;
-- 0x38
...
...
hdl/rtl/vme_bus.vhd
View file @
a994813b
...
...
@@ -244,7 +244,7 @@ begin
-- Address modifier decoder
-- Both the supervisor and the user access modes are supported
with
s_AMlatched
select
s_addressingType
<=
A24
when
c_AM_A24_S
_SUP
|
c_AM_A24_S
,
A24
when
c_AM_A24_S
UP
|
c_AM_A24
,
A24_BLT
when
c_AM_A24_BLT
|
c_AM_A24_BLT_SUP
,
A24_MBLT
when
c_AM_A24_MBLT
|
c_AM_A24_MBLT_SUP
,
CR_CSR
when
c_AM_CR_CSR
,
...
...
hdl/testbench/simple_tb/top_tb.vhd
View file @
a994813b
...
...
@@ -1240,16 +1240,16 @@ begin
-- Set ADER
write8_conf
(
x"7_ff73"
,
x"00"
);
write8_conf
(
x"7_ff77"
,
x"20"
);
write8_conf
(
x"7_ff7f"
,
c_AM_A24
_S
&
"00"
);
write8_conf
(
x"7_ff7f"
,
c_AM_A24
&
"00"
);
-- Enable card
write8_conf
(
x"7_fffb"
,
b"0001_0000"
);
read32
(
x"00_20_00_10"
,
c_AM_A24
_S
,
d32
);
read32
(
x"00_20_00_10"
,
c_AM_A24
,
d32
);
assert
d32
=
x"0000_0004"
report
"incorrect read 32"
severity
error
;
read32
(
x"13_20_00_14"
,
c_AM_A24
_S
,
d32
);
read32
(
x"13_20_00_14"
,
c_AM_A24
,
d32
);
assert
d32
=
x"0000_0500"
report
"incorrect read 32"
severity
error
;
...
...
@@ -1259,12 +1259,12 @@ begin
-- Set ADER
write8_conf
(
x"7_ff73"
,
x"00"
);
write8_conf
(
x"7_ff77"
,
x"20"
);
write8_conf
(
x"7_ff7f"
,
c_AM_A24
_S
&
"00"
);
write8_conf
(
x"7_ff7f"
,
c_AM_A24
&
"00"
);
-- Enable card
write8_conf
(
x"7_fffb"
,
b"0001_0000"
);
read32
(
x"00_20_80_04"
,
c_AM_A24
_S
,
d32
);
read32
(
x"00_20_80_04"
,
c_AM_A24
,
d32
);
assert
d32
=
(
31
downto
0
=>
'X'
)
report
"incorrect read 32"
severity
error
;
...
...
@@ -1349,7 +1349,7 @@ begin
end
if
;
-- However, the A24 decoder is not enabled.
read8
(
x"56_00_00_00"
,
c_AM_A24
_S
,
d8
);
read8
(
x"56_00_00_00"
,
c_AM_A24
,
d8
);
if
g_SCENARIO
=
8
then
assert
d8
=
"XXXXXXXX"
report
"unexpected reply (a24s)"
severity
error
;
else
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment