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conv-common-gw
Commit e578169c authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Added support for temperature readout from one wire chip

parent aa7b1aff
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modules/conv_regs.vhd
View file @ e578169c
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : .\conv_regs.vhd
-- Author : auto-generated by wbgen2 from .\conv_regs.wb
-- Created : 08/22/16 15:29:40
-- File : \\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv_regs.vhd
-- Author : auto-generated by wbgen2 from \\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\modules\conv_regs.wb
-- Created : 10/11/16 16:46:39
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE .\conv_regs.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE \\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\modules\conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -84,7 +83,6 @@ entity conv_regs is
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH6TTLPCR'
reg_ch6ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch6ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch6ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH1BLOPCR'
reg_ch1blopcr_o : out std_logic_vector(31 downto 0);
......@@ -120,6 +118,8 @@ entity conv_regs is
reg_tvhr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
reg_tbmr_chan_i : in std_logic_vector(5 downto 0);
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o : out std_logic; --***added manually
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
......@@ -138,8 +138,6 @@ entity conv_regs is
reg_tbcsr_clr_o : out std_logic;
reg_tbcsr_clr_i : in std_logic;
reg_tbcsr_clr_load_o : out std_logic;
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o : out std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH1LTSCYR'
reg_ch1ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH1LTSTLR'
......@@ -201,7 +199,15 @@ entity conv_regs is
-- Port for std_logic_vector field: 'Rear panel input failsafe state' in reg: 'LSR'
reg_lsr_rearfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Switch state' in reg: 'OSWR'
reg_oswr_switches_i : in std_logic_vector(31 downto 0)
reg_mswr_switches_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR'
reg_oswr_switches_i : in std_logic_vector(31 downto 0);---added manually
-- Port for std_logic_vector field: 'LS bits of 1-wire DS18B20U thermometer ID' in reg: '32 least significant bits of DS18B20U'
reg_ds18b20u_id_lsb_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'MS bits of 1-wire DS18B20U thermometer ID' in reg: '32 most significant bits of DS18B20U'
reg_ds18b20u_id_msb_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Temperature from DS18B20 thermometer' in reg: 'Board temperature'
reg_ds18b20u_temp_i : in std_logic_vector(15 downto 0)
);
end conv_regs;
......@@ -255,7 +261,6 @@ begin
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tbcsr_clr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -283,7 +288,6 @@ begin
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tbcsr_clr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
ack_in_progress <= '0';
else
reg_sr_i2c_wdto_load_o <= '0';
......@@ -307,7 +311,6 @@ begin
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tbcsr_clr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -465,7 +468,6 @@ begin
rddata_reg(31 downto 0) <= reg_tvlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010000" =>
if (wb_we_i = '1') then
reg_tvhr_load_o <= '1';
......@@ -497,11 +499,9 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010001" =>
if (wb_we_i = '1') then
end if;
reg_tb_rd_req_p_o <= '1';
rddata_reg(5 downto 0) <= reg_tbmr_chan_i;
rddata_reg(31) <= reg_tbmr_wrtag_i;
rddata_reg(6) <= 'X';
......@@ -531,7 +531,6 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010010" =>
if (wb_we_i = '1') then
end if;
......@@ -542,14 +541,12 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_tbtlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010100" =>
if (wb_we_i = '1') then
end if;
......@@ -580,7 +577,6 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010101" =>
if (wb_we_i = '1') then
reg_tbcsr_clr_load_o <= '1';
......@@ -613,7 +609,6 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010110" =>
if (wb_we_i = '1') then
end if;
......@@ -624,14 +619,12 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch1ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011000" =>
if (wb_we_i = '1') then
end if;
......@@ -662,7 +655,6 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011001" =>
if (wb_we_i = '1') then
end if;
......@@ -673,14 +665,12 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch2ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011011" =>
if (wb_we_i = '1') then
end if;
......@@ -711,7 +701,6 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011100" =>
if (wb_we_i = '1') then
end if;
......@@ -722,14 +711,12 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch3ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011110" =>
if (wb_we_i = '1') then
end if;
......@@ -760,7 +747,6 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011111" =>
if (wb_we_i = '1') then
end if;
......@@ -771,14 +757,12 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch4ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100001" =>
if (wb_we_i = '1') then
end if;
......@@ -809,7 +793,6 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100010" =>
if (wb_we_i = '1') then
end if;
......@@ -820,14 +803,12 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch5ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100100" =>
if (wb_we_i = '1') then
end if;
......@@ -858,7 +839,6 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100101" =>
if (wb_we_i = '1') then
end if;
......@@ -869,14 +849,12 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch6ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100111" =>
if (wb_we_i = '1') then
end if;
......@@ -907,7 +885,6 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101000" =>
if (wb_we_i = '1') then
end if;
......@@ -919,11 +896,44 @@ begin
rddata_reg(31 downto 26) <= reg_lsr_rearfs_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_oswr_switches_i;
rddata_reg(31 downto 0) <= reg_mswr_switches_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ds18b20u_id_lsb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ds18b20u_id_msb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= reg_ds18b20u_temp_i;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
......@@ -1023,10 +1033,12 @@ begin
-- Front panel INV-TTL input state
-- Rear panel input state
-- Front panel input failsafe state
-- Front panel inverter input failsafe state
-- Rear panel input failsafe state
-- Switch state
-- LS bits of 1-wire DS18B20U thermometer ID
-- MS bits of 1-wire DS18B20U thermometer ID
-- Temperature from DS18B20 thermometer
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
modules/conv_regs.wb
View file @ e578169c
......@@ -30,6 +30,9 @@
-- last changes:
-- 03-05-2014 Theodor Stana Added GPL header
-- 31-07-2014 Theodor Stana Added MSWR & LSR registers
-- Denia Bouhired Added separate pulse counters for TTL and BLO pulses
-- 11-10-2016 Denia Bouhired Added thermometer registers one 16 bit for temperature read out
-- 2 for LSBs and MSBs of 64-bit ID
--==============================================================================
-- TODO: -
--==============================================================================
......@@ -913,5 +916,48 @@ peripheral {
access_bus = READ_ONLY;
};
};
-- 32 LS Bits of 64 bit ID of 1-Wire thermometer
reg {
name = "32 least significant bits of DS18B20U";
description = "32 LS bits of 1-wire thermometer ID";
prefix = "DS18B20U_ID_LSB";
field {
name = "LS bits of 1-wire DS18B20U thermometer ID";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-- 32 MS Bits of 64 bit ID of 1-Wire thermometer
reg {
name = "32 most significant bits of DS18B20U";
description = "32 MS bits of 1-wire thermometer ID";
prefix = "DS18B20U_ID_MSB";
field {
name = "MS bits of 1-wire DS18B20U thermometer ID";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-- 16 bit temperature
reg {
name = "Board temperature";
description = "raw temperature data from the one wire DS18B20U. The register is 2-bytes long; it translates to oC as follows: temp = ((byte1 << 8) | byte0) / 16.0";
prefix = "DS18B20U_temp";
field {
name = "Temperature from DS18B20 thermometer";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
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