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conv-common-gw
Commit ccaffebc authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Previsous version had some bugs. Bugs fixed plus modified FSM by removing… 

Previsous version had some bugs. Bugs fixed plus modified FSM by removing temp_rise processing from FSM and generating it from separate process.
parent ba9673e5
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modules/conv_dyn_burst_ctrl.vhd
View file @ ccaffebc
......@@ -12,27 +12,23 @@
--
-- Description:
-- This module serves as a burst mode controller. When pulses of
-- pre-defined length (250 ns) arrive, depending on the frequency, the
-- pre-defined length (250 ns or 1.2us) arrive, depending on the frequency, the
-- module will allow the pulse to go through for a pre-defined amount of
-- time, before going into pulse rejection mode. The rejection lasts for
-- the time it takes for the "temperature" to go below the set upper limit
-- g_max_temp. For each frequency, the time of failure selected
-- corresponds to the time it takes to reach g_max_temp for pulses at the
-- same frequency. This is mapped onto the temperature rise caused by a
-- single pulse (the maximum rise at 2MHz max frequency is
-- g_1_pulse_temp_rise) of the corresponding period. The array of values
-- representing the thermal properties at the pulse level is given as the
-- array of integers temp_decre_step. This array of values is
-- generated in pre-processing via python script (Link??). These values
-- correspond to the thermal model of the board components defined at
-- the pulse level.
-- the time it takes for the "temperature" to reach the upper limit
-- g_max_temp. For each frequency, the time of failure selected
-- corresponds to the time it takes to reach g_max_temp for pulses of a given
-- frequency.
-- The array of values representing the thermal properties at the pulse level
-- is given as the array of integers temp_decre_step. This array of values is
-- generated in pre-processing via python script (*link to be added*). These
-- values correspond to the thermal model of the board components. They are
-- different for short 250ns pulses and long 1.2us pulses.
-- Any modification to the board specification which would change the
-- high frequency operation behaviour, would require changing the 3
-- parameters g_1_pulse_temp_rise, g_max_temp and t_temp_decre_step. These
-- are generated using the Python file (link?)
-- are generated using the Python file (*link to be added*).
-- dependencies:
......@@ -61,23 +57,26 @@ use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
--============================================================================
--ENTITY DECLARATION
--============================================================================
----------------------------------------------------------------------------
-- ENTITY DECLARATION
----------------------------------------------------------------------------
entity conv_dyn_burst_ctrl is
generic
(
-- Fixed pulse width set to 5 clock cycles = 5* 50ns = 250 ns
-- Fixed pulse width
g_pwidth : natural range 2 to 40 := 5;
-- Array of decrement values derived from the choses thermal model
-- The following t_temp_decre_step values correspond to "1s, 6.5s, 10s, 26s,
-- 36.66s and continuous" for pulsing for frequencies
-- 2MHz, 1.33MHz, 1MHz, 800kHz, 667 kHz and 571kHz respectively.
g_temp_decre_step : t_temp_decre_step :=
(0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
(0,0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
--Scaled temperature rise resulting from single pulse.
--Scaled temperature rise resulting from a single pulse.
g_1_pulse_temp_rise :in unsigned (19 downto 0) := x"01388"; --5000
-- Scaled maximum temperature ceiling before pulse inhibition
-- is necessary to lower temperature
-- Scaled maximum temperature ceiling for pulse inhibition
g_max_temp :in unsigned (39 downto 0) := x"02540BE400" --10^10
);
port
......@@ -94,7 +93,7 @@ entity conv_dyn_burst_ctrl is
pulse_r_edge_p_i : in std_logic;
pulse_f_edge_p_i : in std_logic;
-- Dynamic,temperature controlled ouput pulse train.
-- Dynamic temperature-controlled ouput pulse train.
pulse_burst_o : out std_logic;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
......@@ -103,12 +102,11 @@ entity conv_dyn_burst_ctrl is
);
end entity conv_dyn_burst_ctrl;
-----------------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- ARCHITECTURE
-----------------------------------------------------------------------------------------
----------------------------------------------------------------------------
architecture behav of conv_dyn_burst_ctrl is
--type t_temp_decre_step is array (0 to 5) of integer;
type t_state is (
IDLE,
......@@ -116,62 +114,32 @@ entity conv_dyn_burst_ctrl is
PULSE_REJECT
);
--The following t_temp_decre_step values correspond to "1s, 6.5s, 10s, 26s, 36.66s and continuous"
--for pulsing for frequencies 2MHz, 1.33MHz, 1MHz, 800kHz, 667 kHz and 571kHz respectively.
--signal temp_decre_step : t_temp_decre_step := (0, 769, 31, 104, 14, 82);
signal burst_ctrl_rst : std_logic;
signal pulse_train_in : std_logic;
signal temp_rise : unsigned (39 downto 0) ;
signal single_cycle_cnt : integer;
signal n_cycle_cnt : integer range 0 to g_temp_decre_step'LENGTH;
signal pulse_train_in_d0 : std_logic;
signal pulse_train_in_r_edge_p : std_logic;
signal pulse_train_in_f_edge_p : std_logic;
signal thermal_array_lgth :natural := 6;
signal n_cycle_cnt : integer range 1 to g_temp_decre_step'LENGTH;
signal thermal_array_lgth :natural := 7;
signal thermal_res : natural; -- thermal resolution in clock cycles
signal state : t_state;
signal nxt_state : t_state;
constant thermal_res : natural := g_pwidth; -- thermal resolution in clock cycles
signal s_pulse_reject, s_pulse_repeat : std_logic;
begin
thermal_array_lgth <= 6 when g_pwidth = 5 else 15;
thermal_array_lgth <= 7 when g_pwidth = 5 else 16;
thermal_res <= g_pwidth; --Resolution depends on i/p pulse width
pulse_train_in <= '0' when burst_ctrl_rst = '1' else pulse_burst_i and en_i;
pulse_burst_o <= pulse_train_in;
--Process to count in n clk cycles steps
p_n_cycle_cnt : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
single_cycle_cnt <= 1;
n_cycle_cnt <= 1;
else
--reset counters in the event of a new pulse only when pulse rejection is not activ
if (pulse_r_edge_p_i = '1' or pulse_f_edge_p_i = '1') and burst_ctrl_rst = '0' then
single_cycle_cnt <= 1;
n_cycle_cnt <= 1;
--When no pulse is being repeated, whether because pulse is off or because it is being rejected
else
single_cycle_cnt <= single_cycle_cnt + 1; --count clk cycles
if single_cycle_cnt = thermal_res then
if n_cycle_cnt < thermal_array_lgth then
n_cycle_cnt <= n_cycle_cnt + 1; --increment every n=thermal_res clk cycles
end if;
single_cycle_cnt <= 1;
end if;
end if;
end if;
end if;
end process p_n_cycle_cnt;
-- Output from module depends on burst_ctrl_rst and en_i
---------------------------------------------------------
pulse_burst_o <= '0' when burst_ctrl_rst = '1' else pulse_burst_i and en_i;
-----------------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Finite State Machine FSM
-- Finite State Machine to control pulse repetition as a function of rising board temperature.
-- The FSM uses a temp_rise counter
-----------------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Finite State Machine to control pulse repetition as a function of rising
-- board temperature. The FSM relies on temp_rise counter for state transitions
-----------------------------------------------------------------------------
-- Process to trigger state transitions
----------------------------------------
......@@ -189,58 +157,49 @@ entity conv_dyn_burst_ctrl is
-- Process to define FSM states
--------------------------------
p_thermal_fsm_states : process (state, pulse_r_edge_p_i, pulse_f_edge_p_i, temp_rise, n_cycle_cnt )
p_thermal_fsm_states : process (state, pulse_r_edge_p_i, pulse_f_edge_p_i,
n_cycle_cnt, temp_rise, en_i )
begin
case state is
-----------------------------------------------------------------------------------------
-- The FSM is IDLE, when the board is completely "cool", temp_rise =0,
-- and no new pulses arrive after 1.75us from the last one
-----------------------------------------------------------------------------------------
-------------------------------------------------------------------------
-- The FSM is IDLE, when the board is reset
-------------------------------------------------------------------------
when IDLE =>
if pulse_r_edge_p_i = '1' then
if temp_rise >= 0 and temp_rise < g_max_temp then
if en_i = '1' and pulse_r_edge_p_i = '1' then
nxt_state <= PULSE_REPEAT;
else
nxt_state <= PULSE_REJECT;
end if;
nxt_state <= IDLE;
end if;
-----------------------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PULSE_REPEAT pulses are repeated as long as the temperature is below
-- maximum g_max_temp.
-- While the temperature counter temp_rise is above 0, the time between
-- 2 pulses is used to decrement it.
-----------------------------------------------------------------------------------------
-- 2 pulses is used to decrement it, i.e. to cool down.
-------------------------------------------------------------------------
when PULSE_REPEAT =>
if temp_rise <= g_max_temp then
if pulse_r_edge_p_i = '1' then
nxt_state <= PULSE_REPEAT;
elsif temp_rise = 0 and n_cycle_cnt = thermal_array_lgth then
nxt_state <= IDLE;
end if;
else
nxt_state <= PULSE_REJECT;
end if;
-----------------------------------------------------------------------------------------
-----------------------------------------------oo-----------------------
-- PULSE_REJECT applies when a new pulse causes temperature to exceed
-- maximum value
-- i.e. temp_rise >= g_max_temp.
-----------------------------------------------------------------------------------------
------------------------------------------------------------------------
when PULSE_REJECT =>
if temp_rise <= g_max_temp then
if pulse_f_edge_p_i ='1' then
if pulse_f_edge_p_i = '1' and temp_rise <= g_max_temp then
nxt_state <= PULSE_REPEAT;
end if;
else
nxt_state <= PULSE_REJECT;
end if;
when others =>
nxt_state <= IDLE;
end case;
end process p_thermal_fsm_states;
......@@ -248,33 +207,95 @@ entity conv_dyn_burst_ctrl is
-- Process to define FSM outputs
--------------------------------
p_thermal_fsm_outputs : process (state,pulse_r_edge_p_i, pulse_f_edge_p_i, single_cycle_cnt, n_cycle_cnt)
p_thermal_fsm_outputs : process (state, pulse_r_edge_p_i)
begin
-----------------------------------------------------------------------------------------
-- The FSM is IDLE, when the board is completely "cool", temp_rise =0, and no
-- new pulses arrive after 1.75us from the last one
-----------------------------------------------------------------------------------------
-------------------------------------------------------------------------
-- In the idle state all outputs are reset
-------------------------------------------------------------------------
case state is
when IDLE =>
temp_rise <= (others => '0');
burst_ctrl_rst <= '0';
burst_err_p_o <= '0';
s_pulse_reject <= '0';
s_pulse_repeat <= '0';
-----------------------------------------------------------------------------------------
-- PULSE_REPEAT pulses are repeated as long as the temperature is below maximum g_max_temp.
-- While the temperature counter temp_rise is above 0, the time between 2 pulses is used to decrement it.
-----------------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- In PULSE_REPEAT pulses the input pulse is copied to the output and
-- the state flag s_pulse_repeat is set
--------------------------------------------------------------------------
when PULSE_REPEAT =>
burst_err_p_o <= '0';
burst_ctrl_rst <= '0';
s_pulse_repeat <= '1';
s_pulse_reject <= '0';
---------------------------------------------------------------------------
-- PULSE_REJECT sets burst_ctrl_rst to 1 to cutoff the output and sets the
-- error pulse
---------------------------------------------------------------------------
when PULSE_REPEAT =>
when PULSE_REJECT =>
burst_err_p_o <= pulse_r_edge_p_i;
burst_ctrl_rst <= '1';
s_pulse_reject <= '1';
s_pulse_repeat <= '0';
when others =>
burst_ctrl_rst <= '0';
burst_err_p_o <= '0';
s_pulse_reject <= '0';
s_pulse_repeat <= '0';
end case;
end process p_thermal_fsm_outputs;
-- Process to count in n clk cycles steps
-- single_cycle_cnt counts clock cycles. When it reaches the thermal resolution
-- (pulse width dependent) it increments n_cycle_cnt by 1 and single_cycle_cnt
-- is reset to 1 again. n_cycle_cnt is reset to 1 only when a new pulse arrives
-- and pulse output inhibition is not active.
---------------------------------------------------------------------------
p_n_cycle_cnt : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
single_cycle_cnt <= 1;
n_cycle_cnt <= 1;
else
-- Reset counters in the event of a new pulse only
-- when pulse rejection is not active
if (pulse_r_edge_p_i = '1') and burst_ctrl_rst = '0' then
single_cycle_cnt <= 1;
n_cycle_cnt <= 1;
else
--count clk cycles
single_cycle_cnt <= single_cycle_cnt + 1;
if single_cycle_cnt = thermal_res then
if n_cycle_cnt < thermal_array_lgth then
-- increment every n=thermal_res clk cycles
n_cycle_cnt <= n_cycle_cnt + 1;
end if;
single_cycle_cnt <= 1;
end if;
end if;
end if;
end if;
end process p_n_cycle_cnt;
if pulse_f_edge_p_i = '1' then
-- Process to output temperature rise. When a new pulse arrives,
-- temp_rise rises at the falling edge. Between pulses, temp_rise is
-- decremented according to the thermal model.
------------------------------------------------------------------------------
p_temp_rise : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
temp_rise <= (others => '0');
else
if s_pulse_repeat = '1' then
if pulse_f_edge_p_i ='1' then
temp_rise <= temp_rise + g_1_pulse_temp_rise;
else
if temp_rise >= g_temp_decre_step(n_cycle_cnt-1) then
......@@ -283,20 +304,13 @@ entity conv_dyn_burst_ctrl is
temp_rise <= (others => '0');
end if;
end if;
elsif s_pulse_reject = '1' and temp_rise > 0 then
temp_rise <= temp_rise - to_unsigned(g_temp_decre_step(n_cycle_cnt-1), 40);
end if;
end if;
end if;
end process p_temp_rise;
-----------------------------------------------------------------------------------------
-- PULSE_REJECT applies when a new pulse causes temperature to exceed maximum value
--i.e. temp_rise >= g_max_temp.
-----------------------------------------------------------------------------------------
when PULSE_REJECT =>
burst_ctrl_rst <= '1';
burst_err_p_o <= pulse_r_edge_p_i;
temp_rise <= temp_rise - g_temp_decre_step(n_cycle_cnt-1);
end case;
end process p_thermal_fsm_outputs;
end architecture behav;
\ No newline at end of file
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