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conv-common-gw
Commit cba9c6a6 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Updated top file and burt control module with little modifications. NOTE LED… 

Updated top file and burt control module with little modifications. NOTE LED sequence is fixed at certain pattern for bitstream debugging
parent 3833a065
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Showing with 48 additions and 46 deletions
modules/conv_dyn_burst_ctrl.vhd
View file @ cba9c6a6
...@@ -49,10 +49,8 @@ entity conv_dyn_burst_ctrl is ...@@ -49,10 +49,8 @@ entity conv_dyn_burst_ctrl is
generic generic
( (
g_pwidth : natural range 2 to 40 := 5; g_pwidth : natural range 2 to 40 := 5;
-- Duty cycle divider: D = 1/g_duty_cycle_div g_1_pulse_temp_rise :in unsigned (15 downto 0) := x"A410";
g_duty_cycle_div : natural := 18; g_max_temp :in unsigned (39 downto 0) := x"174876E800"
g_1_pulse_energ :in unsigned (15 downto 0) := x"A410";
g_max_temp_rise :in unsigned (39 downto 0) := x"174876E800"
); );
port port
( (
...@@ -64,8 +62,8 @@ entity conv_dyn_burst_ctrl is ...@@ -64,8 +62,8 @@ entity conv_dyn_burst_ctrl is
en_i : in std_logic; en_i : in std_logic;
pulse_burst_i : in std_logic; pulse_burst_i : in std_logic;
temp_rise_c : out unsigned (39 downto 0) ;
pulse_burst_o : out std_logic; pulse_burst_o : out std_logic;
temp_rise_c : out unsigned (39 downto 0) ;
-- Burst error output, pulses high for one clock cycle when a pulse arrives -- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase -- within a burst rejection phase
...@@ -182,13 +180,13 @@ temp_rise_c <=temp_rise; ...@@ -182,13 +180,13 @@ temp_rise_c <=temp_rise;
burst_ctrl_rst <= '1'; burst_ctrl_rst <= '1';
else else
if signed(temp_rise) >= 0 and (signed(temp_rise) <= signed(g_max_temp_rise)) then if signed(temp_rise) >= 0 and (signed(temp_rise) <= signed(g_max_temp)) then
if pulse_burst_i = '0' then if pulse_burst_i = '0' then
burst_ctrl_rst <= '0'; burst_ctrl_rst <= '0';
end if; end if;
if pulse_train_in_r_edge_p = '1' and burst_ctrl_rst /= '1' then -- temperature less than maximum if pulse_train_in_r_edge_p = '1' and burst_ctrl_rst /= '1' then -- temperature less than maximum
temp_rise <= temp_rise + g_1_pulse_energ; temp_rise <= temp_rise + g_1_pulse_temp_rise;
elsif signed(temp_rise) > 0 and pulse_train_in = '0' then --temperature fall between pulses elsif signed(temp_rise) > 0 and pulse_train_in = '0' then --temperature fall between pulses
test <= temp_decre(five_cycle_cnt-1); test <= temp_decre(five_cycle_cnt-1);
...@@ -198,7 +196,7 @@ temp_rise_c <=temp_rise; ...@@ -198,7 +196,7 @@ temp_rise_c <=temp_rise;
temp_rise <= (others => '0'); temp_rise <= (others => '0');
end if; end if;
end if; end if;
elsif (signed(temp_rise) > signed(g_max_temp_rise)) and pulse_train_in = '0' then -- and (pulse_train_in_f_edge_p = '1') then elsif (signed(temp_rise) > signed(g_max_temp)) and pulse_train_in = '0' then -- and (pulse_train_in_f_edge_p = '1') then
burst_ctrl_rst <= '1'; burst_ctrl_rst <= '1';
temp_rise <= temp_rise - temp_decre(five_cycle_cnt-1); temp_rise <= temp_rise - temp_decre(five_cycle_cnt-1);
end if; end if;
......
modules/conv_pulse_gen.vhd
View file @ cba9c6a6
...@@ -69,7 +69,7 @@ entity conv_pulse_gen is ...@@ -69,7 +69,7 @@ entity conv_pulse_gen is
-- Default pulse width (20 MHz clock): 1.2 us -- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us -- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us -- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24; g_pwidth : natural range 2 to 40 := 24;
-- Duty cycle divider: D = 1/g_duty_cycle_div -- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5 g_duty_cycle_div : natural := 5
......
top/conv_common_gw.vhd
View file @ cba9c6a6
...@@ -70,12 +70,12 @@ entity conv_common_gw is ...@@ -70,12 +70,12 @@ entity conv_common_gw is
-- Board ID -- 4-letter ASCII string indicating the board ID -- Board ID -- 4-letter ASCII string indicating the board ID
-- see [1] for example -- see [1] for example
g_board_id : std_logic_vector(31 downto 0); g_board_id : std_logic_vector(31 downto 0) := x"54424c4f";
-- Gateware version -- Gateware version
g_gwvers : std_logic_vector(7 downto 0); g_gwvers : std_logic_vector(7 downto 0) :=x"40";
-- Generate pulse repetition logic with fixed output pulse width -- Generate pulse repetition logic with fixed output pulse width
g_pgen_fixed_width : boolean; g_pgen_fixed_width : boolean := true ;
-- Pulse width at pulse generator output (valid with fixed output pulse width) -- Pulse width at pulse generator output (valid with fixed output pulse width)
g_pgen_pwidth : natural range 2 to 40 := 24; g_pgen_pwidth : natural range 2 to 40 := 24;
g_pgen_pwidth_sh : natural range 2 to 40 := 5; g_pgen_pwidth_sh : natural range 2 to 40 := 5;
...@@ -87,10 +87,11 @@ entity conv_common_gw is ...@@ -87,10 +87,11 @@ entity conv_common_gw is
g_pgen_gf_len : integer := 4; g_pgen_gf_len : integer := 4;
-- Burst-mode-specific generics: -- Burst-mode-specific generics:
-- Maximum number of pulses in burst before forced burst rejection. Number dictated by hardware limitations -- Temperature rise resulting from 250ns pulse
g_burstctrl_max_burst_len : natural := 1000; g_burstctrl_1_pulse_temp_rise :in unsigned (15 downto 0) := x"2670"; -- Check every "g_eval_burst_len" pulses
-- 20000000 corresponds to 1 second timeout, 60000 corresponds to 3ms timeout. When timeout is reached burst rejection may start if necessary else go back to IDLE. Useful when pulses are not frequent.
g_burstctrl_timeout : natural := 200000; -- Maximum temperature allowed (scaled)
g_burstctrl_max_temp :in unsigned (39 downto 0) :=x"02540BE400";
-- Generate logic with pulse counters -- Generate logic with pulse counters
g_with_pulse_cnt : boolean := false; g_with_pulse_cnt : boolean := false;
...@@ -200,12 +201,12 @@ entity conv_common_gw is ...@@ -200,12 +201,12 @@ entity conv_common_gw is
-- TTL, INV-TTL and rear-panel channel inputs, for reflection in line status register -- TTL, INV-TTL and rear-panel channel inputs, for reflection in line status register
line_front_i : in std_logic_vector(g_nr_chans-1 downto 0); line_front_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_inv_i : in std_logic_vector(3 downto 0); line_inv_i : in std_logic_vector(g_nr_inv_chans-1 downto 0);
line_rear_i : in std_logic_vector(g_nr_chans-1 downto 0); line_rear_i : in std_logic_vector(g_nr_chans-1 downto 0);
-- Fail-safe lines, detect invalid or no signal on channel input -- Fail-safe lines, detect invalid or no signal on channel input
line_front_fs_i : in std_logic_vector(g_nr_chans-1 downto 0); line_front_fs_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_inv_fs_i : in std_logic_vector(3 downto 0); line_inv_fs_i : in std_logic_vector(g_nr_inv_chans-1 downto 0);
line_rear_fs_i : in std_logic_vector(g_nr_chans-1 downto 0); line_rear_fs_i : in std_logic_vector(g_nr_chans-1 downto 0);
-- Thermometer line -- Thermometer line
...@@ -319,6 +320,9 @@ architecture arch of conv_common_gw is ...@@ -319,6 +320,9 @@ architecture arch of conv_common_gw is
signal inv_pulse_outp_d0 : std_logic_vector(g_nr_inv_chans-1 downto 0); signal inv_pulse_outp_d0 : std_logic_vector(g_nr_inv_chans-1 downto 0);
signal inv_pulse_outp_fedge_p : std_logic_vector(g_nr_inv_chans-1 downto 0); signal inv_pulse_outp_fedge_p : std_logic_vector(g_nr_inv_chans-1 downto 0);
signal pmisse_p : std_logic_vector(g_nr_chans-1 downto 0); signal pmisse_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_err : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_err_sh : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_outp_err : std_logic_vector(g_nr_chans-1 downto 0);
-- Output enable signals -- Output enable signals
signal global_oen : std_logic; signal global_oen : std_logic;
...@@ -463,7 +467,7 @@ begin ...@@ -463,7 +467,7 @@ begin
generic map generic map
( (
-- Reset time: 50ns * 2 * (10**6) = 100 ms -- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time => 2*(10**4) ---change back to 6 g_reset_time => 2*(10**6)
) )
port map port map
( (
...@@ -552,7 +556,7 @@ end generate gen_no_man_trig; ...@@ -552,7 +556,7 @@ end generate gen_no_man_trig;
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate gen_pulse_chan_logic : for i in 0 to 5 generate --g_nr_chans-1 generate
-- Synchronize the asynchronous trigger input into the 20 MHz clock -- Synchronize the asynchronous trigger input into the 20 MHz clock
-- domain before passing it to the glitch filter -- domain before passing it to the glitch filter
...@@ -677,7 +681,7 @@ end generate gen_pulse_cnt; ...@@ -677,7 +681,7 @@ end generate gen_pulse_cnt;
trig_a_i => trig_pgen(i), trig_a_i => trig_pgen(i),
pulse_err_p_o => pmisse_p(i), pulse_err_p_o => pulse_outp_err (i),
pulse_o => pulse_outp_1200ns(i) pulse_o => pulse_outp_1200ns(i)
); );
...@@ -705,22 +709,21 @@ end generate gen_pulse_cnt; ...@@ -705,22 +709,21 @@ end generate gen_pulse_cnt;
trig_a_i => trig_pgen(i), trig_a_i => trig_pgen(i),
pulse_err_p_o => open, --pmisse_p(i), pulse_err_p_o => pulse_outp_err_sh (i), --pmisse_p(i),
pulse_o => pulse_outp_sh(i) pulse_o => pulse_outp_sh(i)
); );
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- Instantiate burst control block for the channel -- Instantiate burst control block for the channel
cmp_burst_ctrl : conv_burst_ctrl cmp_burst_ctrl : conv_dyn_burst_ctrl
generic map generic map
( (
g_pwidth => c_pgen_pwidth_sh, g_pwidth => c_pgen_pwidth_sh,
g_duty_cycle_div => g_pgen_duty_cycle_div,
g_max_burst_len => g_burstctrl_max_burst_len, g_1_pulse_temp_rise => g_burstctrl_1_pulse_temp_rise,
g_burst_timeout => g_burstctrl_timeout g_max_temp => g_burstctrl_max_temp
) )
port map port map
( (
...@@ -729,13 +732,15 @@ end generate gen_pulse_cnt; ...@@ -729,13 +732,15 @@ end generate gen_pulse_cnt;
en_i => '1', en_i => '1',
pulse_burst_i => pulse_outp_sh(i), pulse_burst_i => pulse_outp_sh(i),
pulse_burst_o => pulse_outp_250ns(i), pulse_burst_o => pulse_outp_250ns(i),
burst_err_p_o => open temp_rise_c => open,
burst_err_p_o => burst_outp_err (i)
); );
pulse_outp(i) <= pulse_outp_1200ns(i) when burst_en_n_i='1' else pulse_outp_250ns(i); pulse_outp(i) <= pulse_outp_1200ns(i) when burst_en_n_i='1' else pulse_outp_250ns(i);
pmisse_p(i) <= pulse_outp_err (i) when burst_en_n_i='1' else pulse_outp_err_sh(i) or burst_outp_err(i);
----------------------------------------------------------------------------------- -----------------------------------------------------------------------------------
...@@ -782,7 +787,7 @@ end generate gen_pulse_chan_logic; ...@@ -782,7 +787,7 @@ end generate gen_pulse_chan_logic;
-- Process to flash INV-TTL LEDs on the falling edge of the INV-TTL input -- Process to flash INV-TTL LEDs on the falling edge of the INV-TTL input
-- LED flash length: 26 ms -- LED flash length: 26 ms
gen_inv_ttl_leds : for i in 0 to 3 generate gen_inv_ttl_leds : for i in 0 to g_nr_inv_chans-1 generate
-- INV-TTL outputs -- INV-TTL outputs
inv_pulse_outp(i) <= inv_pulse_i_n(i); inv_pulse_outp(i) <= inv_pulse_i_n(i);
......
top/conv_common_gw_pkg.vhd
View file @ cba9c6a6
...@@ -76,17 +76,20 @@ package conv_common_gw_pkg is ...@@ -76,17 +76,20 @@ package conv_common_gw_pkg is
g_pgen_fixed_width : boolean; g_pgen_fixed_width : boolean;
-- Pulse width at pulse generator output (valid with fixed output pulse width) -- Pulse width at pulse generator output (valid with fixed output pulse width)
g_pgen_pwidth : natural range 2 to 40 := 24; --**DB: was 20 to 40 g_pgen_pwidth : natural range 2 to 40 := 24; --**DB: was 20 to 40
g_pgen_pwidth_sh : natural range 2 to 40 := 5;
-- Duty cycle divider ratio for pulse generator -- Duty cycle divider ratio for pulse generator
-- output pulse will be limited to 1/g_pgen_duty_cycle_div -- output pulse will be limited to 1/g_pgen_duty_cycle_div
g_pgen_duty_cycle_div : natural := 200; g_pgen_duty_cycle_div : natural := 200;
g_pgen_duty_cycle_div_sh : natural range 2 to 300 := 2;
-- Pulse generator glitch filter length in number of clk_20_i cycles -- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4; g_pgen_gf_len : integer := 4;
-- Burst-mode-specific generics: -- Burst-mode-specific generics:
-- Maximum number of pulses in burst before forced burst rejection. Number dictated by hardware limitations -- Temperature rise resulting from 250ns pulse
g_burstctrl_max_burst_len : natural := 4; g_burstctrl_1_pulse_temp_rise :in unsigned (15 downto 0); -- Check every "g_eval_burst_len" pulses
-- 20000000 corresponds to 1 second timeout, 60000 corresponds to 3ms timeout. When timeout is reached burst rejection may start if necessary else go back to IDLE. Useful when pulses are not frequent.
g_burstctrl_timeout : natural := 200000; -- Maximum temperature allowed (scaled)
g_burstctrl_max_temp :in unsigned (39 downto 0);
-- Generate logic with pulse counters -- Generate logic with pulse counters
g_with_pulse_cnt : boolean := false; g_with_pulse_cnt : boolean := false;
...@@ -285,23 +288,18 @@ package conv_common_gw_pkg is ...@@ -285,23 +288,18 @@ package conv_common_gw_pkg is
-- Controller for burst mode operation with configurable maximum pulse burst length and timeout -- Controller for burst mode operation with configurable maximum pulse burst length and timeout
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
component conv_burst_ctrl is component conv_dyn_burst_ctrl is
generic generic
( (
-- Short pulse width, in number of clk_i cycles -- Short pulse width, in number of clk_i cycles
-- Default short pulse width (20 MHz clock): 250 ns = 5 clk cycles -- Default short pulse width (20 MHz clock): 250 ns = 5 clk cycles
g_pwidth : natural range 2 to 40 := 5; g_pwidth : natural range 2 to 40 := 5;
-- Duty cycle divider: D = 1/g_duty_cycle_div -- Temperature rise resulting from with 250ns pulse
g_duty_cycle_div : natural := 200; g_1_pulse_temp_rise :in unsigned (15 downto 0); -- Check every "g_eval_burst_len" pulses
-- Number of pulses allowed before decision is made on whether to continue burst
-- Maximum number of pulses that can be received at the worst case 2MHz scenario
g_max_burst_len : natural := 1000; -- Check every "g_eval_burst_len" pulses
-- Burst is evaluated after g_max_burst_len or after a timeout g_burst_timeout set to 1 s. -- Maximum temperature allowed (scaled)
g_burst_timeout : natural := 200000 -- 20000000 corresponds to 1 second timeout g_max_temp :in unsigned (39 downto 0) := x"174876E800"
-- 60000 corresponds to 3ms timeout
); );
port port
( (
...@@ -312,7 +310,9 @@ package conv_common_gw_pkg is ...@@ -312,7 +310,9 @@ package conv_common_gw_pkg is
-- Enable input, pulse generation is enabled when '1' -- Enable input, pulse generation is enabled when '1'
en_i : in std_logic; en_i : in std_logic;
pulse_burst_i : in std_logic; pulse_burst_i : in std_logic;
pulse_burst_o : out std_logic; pulse_burst_o : out std_logic;
temp_rise_c : out unsigned (39 downto 0) ;
-- Burst error output, pulses high for one clock cycle when a pulse arrives -- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase -- within a burst rejection phase
...@@ -320,8 +320,7 @@ package conv_common_gw_pkg is ...@@ -320,8 +320,7 @@ package conv_common_gw_pkg is
); );
end component conv_dyn_burst_ctrl;
end component conv_burst_ctrl;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Converter board control registers -- Converter board control registers
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
......
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