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conv-common-gw
Commit 4b29f817 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Doc: Updated hdl guide for release 4.0 of the gateware

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doc/conv-common-gw.bib
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......@@ -21,8 +21,14 @@
note = {\url{http://www.ohwr.org/projects/conv-common-gw/repository}}
}
@misc{bib:doulos-counter,
title = {{Repository for converter board common gateware}},
note = {\url{https://www.doulos.com/knowhow/fpga/fastcounter/}}
}
@misc{board-id,
title = {{Board IDs for level conversion circuits}},
title = {{A counter for fast events, using a Flancter}},
note = {\url{http://www.ohwr.org/projects/conv-common-gw/wiki/Board-id}}
}
......
doc/conv-common-gw.tex
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......@@ -182,15 +182,15 @@ and despite their seemingly dedicated name, they are also general-purpose switch
time of writing of this document. Therefore, they are considered as \textit{other switches},
due to the fact they do not appear on the CONV-TTL-BLO.
The state of the general-purpose switches can be read from the status register
(SR -- see Appendix~\ref{app:conv-regs-sr}), and the state of the MultiCast
switches can be read from the other switches register (OSWR -- see Appendix~\ref{app:conv-regs-oswr}).
(SR -- see Appendix~\ref{app:conv-regs-SR}), and the state of the MultiCast
switches can be read from the other switches register (OSWR -- see Appendix~\ref{app:conv-regs-OSWR}).
A total of 32 dedicated switches can be implemented on converter boards and mapped to the OSWR, should
they be required. This number-of-32 constraint is imposed by the number of bits in the OSWR.
Table~\ref{tbl:switches} summarizes the switches on converter boards.
\begin{table}[h]
\begin{table}[ht]
\caption{\label{tbl:switches} Switches on converter boards}
\rowcolors{2}{white}{gray!25}
\centerline {
......@@ -199,10 +199,10 @@ Table~\ref{tbl:switches} summarizes the switches on converter boards.
\multicolumn{1}{c}{\textbf{Name}} & \multicolumn{1}{c}{\textbf{Comments}} \\
\hline
General-purpose & Eight switches that \textit{should} be implemented on all converter boards.
Read their state from the SR.SWITCHES field (see Appendix~\ref{app:conv-regs-sr}) \\
Read their state from the SR.SWITCHES field (see Appendix~\ref{app:conv-regs-SR}) \\
Other & Dedicated switches for specific converter boards.
y Read their state from the OSWR register
(see Appendix~\ref{app:conv-regs-oswr}) \\
(see Appendix~\ref{app:conv-regs-OSWR}) \\
\hline
\end{tabular}
}
......@@ -262,7 +262,7 @@ an external reset is received. The external reset can come from one of two sourc
\begin{itemize}
\item the VME system reset pin
\item a write to the CR.RST bit, after having been previously unlocked by a write to the
CR.RST\_UNLOCK bit (see Appendix~\ref{app:conv-regs-cr})
CR.RST\_UNLOCK bit (see Appendix~\ref{app:conv-regs-CR})
\end{itemize}
The \textit{conv\_reset\_gen} component is clocked from \textit{clk\_20\_i}, so the reset
......@@ -355,15 +355,12 @@ For information on the module's implementation, consult its documentation in the
Figure~\ref{fig:pulse-cnt} presents the implementation of the pulse counters.
When a pulse arrives on either the TTL or blocking side, it is resynchronized
in the 20~MHz clock domain and passed through a rising edge detector. When
a rising edge occurs on the pulse, the counter is incremented by one and stored
to the channel pulse counter register. There are two counters implemented separately for TTL
in the 20~MHz clock domain and passed to a \textit{fast counter} module. Indeed, at high frequencies it was found that internal counters need to be able to cope with high frequency triggers howvwer short. A \textit{Flancter} based counter is therefore used~\cite{bib:doulos-counter}. When
a rising edge occurs on the pulse, the result of the counter is stored
to the channel pulse counter register. On v4 release of the gateware\footnotemark\footnotetext{On preceding releases, there was a single counter per channel, aggregating both types of pulses.}, there are two counters implemented separately for TTL
and BLO outputs of each channel (CHxTTLPCR and CHxBLOPCR -- see Appendix~\ref{app:conv-regs}).
Since the counters are incremented after the OR gate, the \textit{line\_front\_i} and \textit{line\_
rear\_i} are ANDed with the synched rising edge of the input line to determine whether the input
is a ttl or a blo signal. The corresponding counters are incremented accordingly. Figure~\ref{
fig:pulse-cnt} presents the implementation for the TTL case only, the same is duplicated for the
Figure~\ref{fig:pulse-cnt} presents the implementation for the TTL case only, the same is duplicated for the
blocking counter.
The pulse counter register can be written via the \textit{conv\_regs} component as a
......@@ -409,7 +406,7 @@ The two counters implemented are:
\end{itemize}
The TAI counter can be loaded with a new value by writing the TVLR and TVHR registers
(see Appendix~\ref{app:conv-regs-tvlr} and~\ref{app:conv-regs-tvhr}). A load of either
(see Appendix~\ref{app:conv-regs-TVLR} and~\ref{app:conv-regs-TVHR}). A load of either
of these registers will reset the internal cycles counter.
Note that due to the synchronization logic, rising edge detector and the latching of the
......@@ -453,7 +450,7 @@ advance on read or write requests from the buffer. While a read can not be perfo
buffer is empty, a write to a full buffer will start overwriting old timestamps.
For converter board designs, a caution should be put in place. Because the TBMR
register (see Appendix~\ref{app:conv-regs-tbmr}) causes the read pointer to advance,
register (see Appendix~\ref{app:conv-regs-TBMR}) causes the read pointer to advance,
it should be the last register read in a readout cycle. Otherwise, the values of the
other tag buffer registers will return the next sample in the tag buffer.
......@@ -509,6 +506,11 @@ Moreover, v4 boards, give the possibility to select pulse width at the output vi
Figure~\ref{fig:pulse-out-sel} shows how the output is selected depending on whether \textit{burst\_en\_n\_i} is activated or not, and also on which pulse width is selected (options are for \textit{SHORT} and \textit{LONG} pulses).
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-out-select}}
\caption{\label{fig:pulse-out-sel} Pulse repetition output selection}
\end{figure}
\subsubsection{Pulse generator}
\label{subsec:pulse-gen}
%------------------------------------------------------------------------------
......@@ -544,8 +546,7 @@ resets
the input flip-flop and goes into the rejection state.
If any pulses arrive either during the generation state, or the rejection state, the error output
is set high for one clock cycle. This type of error is identified as a \textit{FLIM\_ERR\_p},
because they are to do with the maximum allowed frequency being reached.
is set high for one clock cycle. This type of error is identified as a \textit{flim\_err\_p}. It is the result of the maximum allowed frequency being reached.
\begin{figure}
\centerline{\includegraphics[width=\textwidth]{fig/pulse-gen-operation}}
......@@ -566,19 +567,23 @@ The time at which the rejection starts depends on the frequency of the pulses co
are rejected earlier. The lower the frequency the longer are repetition times.
The information relating repetition frequency and repetition times is embedded inside the FPGA and is generated in pre-processing and fed as a generic to the entity. The values used for a given thermal model is an array of constant values input as the \textit{g\_temp\_decre\_step} generic.
They differ for the SHORT and LONG pulse implementations. Appendix~\ref{app:} shows how these values can be generated in pre-processing.
%They differ for the SHORT and LONG pulse implementations. Appendix~\ref{app:} shows how these values can be generated in pre-processing.
In terms of gateware implementation, the \textit{conv\_dyn\_burst\_ctrl}, module uses a finite
In terms of gateware implementation, see Fig.\ref{fig:burst_ctrl}, the \textit{conv\_dyn\_burst\_ctrl}, module uses a finite
state machine (FSM) to handle transitions between pulse repetition and pulse rejection depending
on the \textit{temp\_rise} counter value.
The FSM is triggered by pulse signals \textit{pulse\_r\_edge\_p\_i} and \textit{pulse\_f\_edge\_p\_i}
that had been generated as a result of synchronisation in the \textit{Pulse Generator} block. The
that had been generated as a result of synchronisation inside the \textit{Pulse Generator} block. The
FSM outputs a \textit{burst\_ctrl\_rst} signal as a select signal to a multiplexer. The block's output replicates the input or clears it depending on the status of the \textit{burst\_ctrl\_rst} signal.
An pulse is generated every time a pulse is missed. This is the \textit{frequency watchdog error}, \textit{FWDG\_ERR\_p}, which signifies that the board has started to miss pulses
An error pulse is generated every time a pulse is missed. This is the \textit{frequency watchdog error}, \textit{fwdg\_err\_p}, which signifies that the board has started to miss pulses in order to limit temperature rise.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/burst-ctrl}}
\caption{\label{fig:burst_ctrl} Dynamic burst controller block}
\end{figure}
%------------------------------------------------------------------------------
\subsection{Pulse LED control}
......
doc/conv-regs.tex
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......@@ -276,7 +276,7 @@ RST\_UNLOCK
\item \begin{small}
{\bf
RST
} [\emph{read/write}]: Reset bit - active only if RST_UNLOCK is 1
} [\emph{read/write}]: Reset bit - active only if RST\_UNLOCK is 1
\\
1 -- initiate logic reset \\ 0 -- no reset
\end{small}
......
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